IBM 150 Manuale Utente
50
RS/6000 43P 7043 Models 150 and 260 Handbook
The RS/6000 43P 7043 Model 150 is designed to allow for system growth in
memory, disk, and media devices as the customer’s needs grow. By
combining AIX reliability and function with industry standard bus
architectures, the Model 150 offers exceptional value for multi-user
applications and provides an excellent solution in the entry to mid-range
workstation marketplace.
memory, disk, and media devices as the customer’s needs grow. By
combining AIX reliability and function with industry standard bus
architectures, the Model 150 offers exceptional value for multi-user
applications and provides an excellent solution in the entry to mid-range
workstation marketplace.
3.1.1 Standard Features
In this section, the standard features of the Model 150 and their most
important characteristics are described.
important characteristics are described.
3.1.1.1 Processor Subsystem
The PCI-based IBM RS/6000 43P Model 150 features the PowerPC 604e
microprocessor with the internal clock speed of 375 MHz. With the internal
processor clock to system bus clock frequency ratio set at 9:2, the system
bus is run at 83 MHz. The processor 604e can support bus clock ratios of 1:1,
3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2 and 5:1.
The PCI-based IBM RS/6000 43P Model 150 features the PowerPC 604e
microprocessor with the internal clock speed of 375 MHz. With the internal
processor clock to system bus clock frequency ratio set at 9:2, the system
bus is run at 83 MHz. The processor 604e can support bus clock ratios of 1:1,
3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2 and 5:1.
The 604e integrated L1 cache is split into separate instruction and data
caches. Each of them contains 32 KB four-way set associative data arrays
organized as 32-byte cache lines with no sectoring.
caches. Each of them contains 32 KB four-way set associative data arrays
organized as 32-byte cache lines with no sectoring.
The Model 150 L2 cache subsystem consists of a L2 cache controller and L2
memory. L2 cache memory consists of on-board Tag-Ram and 1 MB parity
synchronous pipelined burst SRAM.
memory. L2 cache memory consists of on-board Tag-Ram and 1 MB parity
synchronous pipelined burst SRAM.
The Model 150 has two cache copy-back write buffers.
3.1.1.2 System Planar Board
One planar is installed in every 7043-150. It provides the system bus and
card connections for the riser card, a voltage regulator and clock module, four
memory DIMM slots. Power supply connections, I/O connections, and a
pin-grid array socket for the PowerPC processor. Only single processor
boards are available.
One planar is installed in every 7043-150. It provides the system bus and
card connections for the riser card, a voltage regulator and clock module, four
memory DIMM slots. Power supply connections, I/O connections, and a
pin-grid array socket for the PowerPC processor. Only single processor
boards are available.
Figure 19 on page 51 shows the system board location for a Model 150, Table
5 on page 52 lists the purpose of the various connections.
5 on page 52 lists the purpose of the various connections.