Intel 82558 Manuale Utente

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The 8255x supports latched level triggered interrupts. Interrupts can be shared in the system if the 

software and NOS support this mechanism. The SCB Command and Status words provide the 
necessary interface for interrupt management. The Mask bit in the SCB Command word should be 

set to 1 to disable interrupts at the adapter. Writing this bit to 0 re-enables adapter interrupts. The 

device supports interrupts from multiple sources as defined by the interrupt status bits in the SCB. 
If more than one interrupt source is active, the device interrupt will stay asserted until all bits are 

acknowledged.

Another useful interrupt source is the Software Interrupt (SWI) bit. Setting this bit in the SCB 

Command word generates an interrupt. Setting the corresponding bit in the SCB Status word de-
asserts the interrupt line. Software that need to generate interrupt requests can use this feature. 

However, if the Mask bit and SWI bit are set at the same time, the Mask bit takes precedence. The 

SWI bit will cause an interrupt request to wait. As soon as the Mask bit is de-asserted, the interrupt 
will propagate to the CPU.