Intel 82558 Manuale Utente

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CLK is inactive and 10 mA if it is active. The deep power down state due to PME 
disable is enabled in the EEPROM.

The 82559 provides wake-up capabilities at all power states. At the D0 state, the 82559 provides a 
wake on link status change capability, while wake on interesting packets is operating at the other 

power states: D1, D2, D3

hot

, D3

cold

. 

Note: The 82559 requires a presence of a system power supply to support wake-up capabilities in the 

D3

cold

 state (bit 4 of the PMC register). The OS should follow the following steps listed:

1. Set the RU into the idle state.

2. Issue a configure command to the 82559 setting the wake-up on Magic Packet (except for the 

82559ER as it does not support Magic Packet) and wake on link status change (which is 
supported on 82559ER) as required. If the 82559 has been configured at initialization time as 

required for the power down state, then this step is redundant.

3. Load the programmable filter if wake on interesting packet is required. This command must be 

issued at each entrance to the power down state. It must be the last command issued to the 

82559 by the driver before it is set by the OS to the power down state as shown in the next 

step(s).

4. Wait for the command to be completely executed and the CU is at the idle state.

5. Set the PME enable bit in the PMCSR to the active state (by OS).

6. Set the 82559 to the selected Dx (x > 0) power state (by OS).

Note: Step 6 may be executed together with step 5 (same cycle) but not before. Otherwise, the 82559 will 

issue a redundant power management event. If the deep power down due to PME disable is enabled 

and the 82559 is set into the D3 state while PME is not enabled, the PHY unit will be turned off. 

After the PME enable bit is set to the active state, the PHY is turned on. After link is established, 
the 82559 issues a power management event due to link status change if wake on link status change 

is enabled.

To initiate the wake-up sequence, the software (OS and driver) are expected to follow the steps 

below:

1. OS sets the 82559 to the D0 state.

2. OS is expected to read and clear the PME bit in the PMCSR. If the PME bit is not cleared, the 

82559 will hold the PME# signal active.

3. If the device is set to D0 from D3, initialization of the base address registers are required.

4. The driver should read and clear the PME indication bits in the PMDR. The PME indication 

bits are: link status change bit, Magic Packet bit, and the interesting packet bit. The PME 
status bit in the PMDR may already be cleared by the OS through the PMCSR.

5. The driver should either issue a selective reset command or dump wake-up packet command, 

depending whether the interesting packet bit is set in the PMDR. If the interesting packet bit is 
active, the driver should read the wake-up packet using the port dump wake-up packet 

command.