Intel 82558 Manuale Utente
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
55
Host Software Interface
The PMDR has evolved over time in the various Intel Fast Ethernet controllers. The PMDR bits for
the 82558 and 82559 are described below.
Note: Not all bits are meaningful in the different generations of devices.
For the 82559, PMDR is initialized at alternate reset only and not at PCI reset (unless a PCI reset
occurs with an alternate reset).
Table 31. Power Management Driver Register Location
Upper Word (D31:D16)
Lower Word (D15:D0)
Offset
SCB Command Word
SCB Status Word
Base + 0h
SCB General Pointer
Base + 4h
PORT
Base + 8h
EEPROM Control Register
Reserved
Base + Ch
MDI Control Register
Base + 10h
Early Receive Interrupt Receive Byte Count Register
Base + 14h
PMDR
FC Xon/Xoff
FC Threshold
Early Rx Int
Base + 18h
Table 32. Power Management Driver Register
Bits
Operation
Default
Description
31
Read/
Clear
Clear
0
Valid for 82559 only.
Link Status Change Indication. The link status change bit indicates
change in the link status. Writing a 1 to this bit will clear it.
Link Status Change Indication. The link status change bit indicates
change in the link status. Writing a 1 to this bit will clear it.
30
Read/
Clear
Clear
0
Valid for 82559 (not 82559ER) only.
Magic Packet. This bit is set when a Magic Packet is received regardless
of the Magic Packet Wake-up disable bit in the configuration command
and the PME enable bit in the PMCSR. Writing a 1 to this bit will clear it.
Magic Packet. This bit is set when a Magic Packet is received regardless
of the Magic Packet Wake-up disable bit in the configuration command
and the PME enable bit in the PMCSR. Writing a 1 to this bit will clear it.
29
Read/
Clear
Clear
0
Valid for 82559 only.
Interesting Packet. This bit is set when an interesting packet is received.
The interesting packet is defined by the 82559 packet filters. Writing a 1 to
this bit will clear it.
Interesting Packet. This bit is set when an interesting packet is received.
The interesting packet is defined by the 82559 packet filters. Writing a 1 to
this bit will clear it.
28
Read Only
0
Reserved.
27
Read Write
0
Valid for 82558 B-step only.
TCO Ready. When this bit is set (by the driver), the TCO ready signal on
the TCO interface is active signaling the TCO controller that the 82558 is
idle and ready for a TCO cycle.
TCO Ready. When this bit is set (by the driver), the TCO ready signal on
the TCO interface is active signaling the TCO controller that the 82558 is
idle and ready for a TCO cycle.
26
Read Only
0
Valid for 82558 B-step and 82559 only.
Force TCO Indication.
Force TCO Indication.
25
Read Only
0
Valid for 82558 B-step and 82559 only.
TCO Request. This bit is set to 1 when the 82559 is busy receiving
packets for or transmitting packets from the TCO controller.
TCO Request. This bit is set to 1 when the 82559 is busy receiving
packets for or transmitting packets from the TCO controller.
24
Read/
Clear
(No clear
on 82559)
Clear
(No clear
on 82559)
0
Valid for the 82558 and 82559.
PME Status. This bit is reflects the PME status bit in the PMCSR. It is set
upon a wake-up event, independent of the PME enable bit. Writing a 1 to
this bit clears it. It also clears the PME status bit in the PMCSR and the
PME# signal. Writing a 0 has no effect on the 82558.
PME Status. This bit is reflects the PME status bit in the PMCSR. It is set
upon a wake-up event, independent of the PME enable bit. Writing a 1 to
this bit clears it. It also clears the PME status bit in the PMCSR and the
PME# signal. Writing a 0 has no effect on the 82558.