IBM 10 SP1 EAL4 Manuale Utente
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Vs: Supervisor mode valid bit. Used with MSR[PR] to restrict translation for some block addresses.
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Vp: User mode valid bit. Used with MSR[PR] to restrict translation for some block addresses.
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PP: Protection bits for block.
5.5.2.3.5 Address translation mechanisms
The following simplified flowchart describes the process of selecting an address translation mechanism based
on the MSR settings for instruction (IR) or data (DR) access. For performance measurement, the processor
concurrently starts both Block Address Translation (BAT) and Segment Address Translation. BAT takes
precedence; therefore, if BAT is successful, Segment Address Translation result is not used.
on the MSR settings for instruction (IR) or data (DR) access. For performance measurement, the processor
concurrently starts both Block Address Translation (BAT) and Segment Address Translation. BAT takes
precedence; therefore, if BAT is successful, Segment Address Translation result is not used.
The following sections describe the three address translation mechanisms, and the access controls they
perform.
perform.
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Figure 5-46: Address translation method selection
Figure 5-45: Block Address Translation entry