Gateway 920 Manuale Utente

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Appendix A: Server Specifications
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Interrupts
The following table reflects a typical configuration, but you can change these 
interrupts. Use this information to determine how to program each interrupt. 
The actual interrupt map is defined using configuration registers in the I/O 
controller. I/O Redirection Registers in the I/O APIC are provided for each 
interrupt signal. The signals define hardware interrupt signal characteristics for 
APIC messages sent to local APIC(s).
Important
If you disable an IDE controller to free the interrupt for that 
controller, you must physically unplug the IDE cable from 
the system board. Simply disabling the drive by configuring 
the SSU option does not make the interrupt available.
Interrupt (IRQ)
Description
0
8254 timer
1
Keyboard controller
2
Cascade
3
Serial  port
4
Serial  port
5
[Unassigned]
6
Diskette controller
7
Parallel
8
Real-time clock
9
ACPI  SCI
10
USB
11
Third IDE
12
Mouse controller
13
System interrupt/FERR
14
Primary IDE
15
Secondary IDE