Texas Instruments TMS320DM355 Manuale Utente
www.ti.com
PRODUCT PREVIEW
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
encoder
•
High-Performance Digital Media
System-on-Chip
System-on-Chip
•
External Memory Interfaces (EMIFs)
–
216- and 270-MHz ARM926EJ-S Clock Rate
–
DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
With 256 MByte Address Space (1.8-V I/O)
–
Fully Software-Compatible With ARM9
–
Asynchronous16-/8-bit Wide EMIF (AEMIF)
•
ARM926EJ-S Core
•
Flash Memory Interfaces
–
Support for 32-Bit and 16-Bit (Thumb Mode)
–
NAND (8-/16-bit Wide Data)
Instruction Sets
–
OneNAND(16-bit Wide Data)
–
DSP Instruction Extensions and Single
Cycle MAC
Cycle MAC
•
Flash Card Interfaces
–
ARM Jazelle Technology
–
Two Multimedia Card (MMC) / Secure
–
EmbeddedICE-RT Logic for Real-Time
Digital (SD/SDIO)
Debug
–
SmartMedia
•
ARM9 Memory Architecture
•
Enhanced Direct-Memory-Access (EDMA)
–
16K-Byte Instruction Cache
Controller (64 Independent Channels)
–
8K-Byte Data Cache
•
USB Port with Integrated 2.0 High-Speed PHY
that Supports
that Supports
–
32K-Byte RAM
–
USB 2.0 Full and High-Speed Device
–
8K-Byte ROM
–
USB 2.0 Low, Full, and High-Speed Host
–
Little Endian
•
Three 64-Bit General-Purpose Timers (each
•
Video Processing Subsystem
configurable as two 32-bit timers)
–
Front End Provides:
•
One 64-Bit Watch Dog Timer
•
Hardware IPIPE for Real-Time Image
Processing
Processing
•
Three UARTs (One fast UART with RTS and
CTS Flow Control)
CTS Flow Control)
•
CCD and CMOS Imager Interface
•
Three Serial Port Interfaces (SPI) each with
•
14-Bit Parallel AFE (Analog Front End)
two Chip-Selects
Interface Up to 67.5 MHz
•
One Master/Slave Inter-Integrated Circuit
•
Glueless Interface to Common Video
(I
2
C) Bus™
Decoders
•
BT.601/BT.656 Digital YCbCr 4:2:2
•
Two Audio Serial Port (ASP)
(8-/16-Bit) Interface
–
I2S and TDM I2S
•
Histogram Module
–
AC97 Audio Codec Interface
•
Resize Engine
–
S/PDIF via Software
–
Resize Images From 1/16x to 8x
–
Standard Voice Codec Interface (AIC12)
–
Separate Horizontal/Vertical Control
–
SPI Protocol (Master Mode Only)
–
Two Simultaneous Output Paths
•
Four Pulse Width Modulator (PWM) Outputs
–
Back End Provides:
•
Four RTO (Real Time Out) Outputs
•
Hardware On-Screen Display (OSD)
•
Up to 104 General-Purpose I/O (GPIO) Pins
•
Composite NTSC/PAL video encoder
(Multiplexed with Other Device Functions)
output
•
On-Chip ARM ROM Bootloader (RBL) to Boot
•
8-/16-bit YCC and Up to 18-Bit RGB666
From NAND Flash, MMC/SD, or UART
Digital Output
•
Configurable Power-Saving Modes
•
BT.601/BT.656 Digital YCbCr 4:2:2
•
Crystal or External Clock Input (typically
(8-/16-Bit) Interface
24 MHz or 36 MHz)
•
Supports digital HDTV (720p/1080i)
•
Flexible PLL Clock Generators
output for connection to external
•
Debug Interface Support
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
I
2
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PRODUCT PREVIEW information concerns products in the
Copyright © 2007–2007, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.