Intel 8XC196Lx Manuale Utente

4-5

Address:

Reset State:

0009H

00H

When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending 
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. 
Software can generate an interrupt by setting the corresponding interrupt pending bit.

—

—

AD

EPA0

EPA1

EPA2

EPA3

EPA

x

J1850RX

J1850TX

AD

EPA0

EPA1

EPA2

EPA3

EPA

x

—

—

—

EPA0

EPA1

EPA2

EPA3

EPA

x

7:0

†

Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared 
when processing transfers to the corresponding interrupt vector.

J1850RX

J1850 Receive (LB only)

J1850TX

J1850 Transmit (LB only)

AD

A/D Conversion Complete (LA, LB)

EPA0

EPA Capture/Compare Channel 0

EPA1

EPA Capture/Compare Channel 1

EPA2

EPA Capture/Compare Channel 2

EPA3

EPA Capture/Compare Channel 3

EPA

x

††

Shared EPA Interrupt

††

EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events

†††

, EPA 

0–3 and 8–9 capture/compare overruns, and timer overflows can generate this shared 
interrupt. Write the EPA mask registersto enable the interrupt sources; read the EPA 
pending registers to determine which source caused the interrupt.

†††

87C196LA, LB only.

†

Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For 
compatibility with future devices, write zeros to these bits.