Intel 8XC196Lx Manuale Utente

Intel

8XC196L

X SUPPLEMENT

vi

FIGURES

Figure

Page

x Block Diagram ............................................................................................2-2

Clock Circuitry (87C196LA, LB Only) ...........................................................................2-3

Internal Clock Phases (Assumes PLL is Bypassed).....................................................2-4

Effect of Clock Mode on Internal CLKOUT Frequency.................................................2-5

Unerasable PROM 1 (USFR1) Register (LA, LB Only) ................................................2-6

Register File Address Map ...........................................................................................3-3

Interrupt Mask (INT_MASK) Register...........................................................................4-3

Interrupt Mask 1 (INT_MASK1) Register......................................................................4-4

Interrupt Pending (INT_PEND) Register ......................................................................4-5

Interrupt Pending 1 (INT_PEND1) Register .................................................................4-6

PTS Select (PTSSEL) Register ....................................................................................4-7

PTS Service (PTSSRV) Register .................................................................................4-8

Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) .......................................5-3

Ports 3 and 4 Internal Structure (87C196LA, LB Only) ................................................5-6

SSIO 0 Clock (SSIO0_CLK) Register...........................................................................6-1

SSIO 1 Clock (SSIO1_CLK) Register...........................................................................6-2

EPA Block Diagram (87C196LA, LB Only)...................................................................7-2

EPA Block Diagram (83C196LD Only) .........................................................................7-3

EPA Interrupt Mask (EPA_MASK) Register .................................................................7-4

EPA Interrupt Mask 1 (EPA_MASK1) Register ............................................................7-4

EPA Interrupt Pending (EPA_PEND) Register.............................................................7-5

EPA Interrupt Pending 1 (EPA_PEND1) Register........................................................7-5

EPA Interrupt Priority Vector Register (EPAIPV)..........................................................7-6

Integrated J1850 Communications Protocol Solution...................................................8-1

J1850 Communications Controller Block Diagram .......................................................8-2

Huntzicker Symbol Definition for J1850........................................................................8-7

Typical VPW Waveform................................................................................................8-7

Bit Arbitration Example .................................................................................................8-8

J1850 Message Frames ...............................................................................................8-9

Huntzicker Symbol Definition for the Normalization Bit ..............................................8-10

Definition for Start and End of Frame Symbols ..........................................................8-11

IFR Type 1 Message Frame.......................................................................................8-12

IFR Type 2 Message Frame.......................................................................................8-13

IFR Type 3 Message Frame.......................................................................................8-13

J1850 Transmit Message Structure............................................................................8-14

J1850 Transmitter (J_TX) Register ............................................................................8-14

J1850 Receive Message Structure.............................................................................8-15

J1850 Receiver (J_RX) Register ................................................................................8-15

J1850 Command (J_CMD) Register ..........................................................................8-17

J1850 Configuration (J_CFG) Register ......................................................................8-18

J1850 Delay (J_DLY) Register ...................................................................................8-20

J1850 Status (J_STAT) Register................................................................................8-21

Reset Source (RSTSRC) Register ...............................................................................9-1

Clock Circuitry (87C196LA, LB Only) .........................................................................10-2