Intel 8XC196Lx Manuale Utente
8XC196L
X SUPPLEMENT
8-6
8.3.2.1
Clock Prescaler
Because the 87C196LB microcontroller can operate at a variety of input frequencies (F
XTAL
1
), the
clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that
the J1850 peripheral is clocked at the proper operating frequency. This is accomplished through
the programmable clock prescaler bits, PRE1:0 in the J_CFG register (Figure 8-17 on page 8-18).
The prescale bits support input frequencies of 8, 12, 16, and 20 MHz on the XTAL1 pin. With
the phase-locked loop (PLL) circuitry enabled, the prescale bits can support input frequencies of
4, 6, 8, and 10 MHz on the XTAL1 pin.
the J1850 peripheral is clocked at the proper operating frequency. This is accomplished through
the programmable clock prescaler bits, PRE1:0 in the J_CFG register (Figure 8-17 on page 8-18).
The prescale bits support input frequencies of 8, 12, 16, and 20 MHz on the XTAL1 pin. With
the phase-locked loop (PLL) circuitry enabled, the prescale bits can support input frequencies of
4, 6, 8, and 10 MHz on the XTAL1 pin.
Table 8-3 details the relationships between the input frequency, the configuration of PLL, the in-
ternal clock frequency, and the prescaler bits.
ternal clock frequency, and the prescaler bits.
8.3.2.2
Digital Filter
To automatically reject noise spikes of 8 µs or less in duration, the J1850 controller uses a digital
filter between the RXJ1850 input pin and the symbol synchronization logic.
filter between the RXJ1850 input pin and the symbol synchronization logic.
A noise spike is defined as an active or passive state pulse that is shorter in duration than a valid
receive symbol at that state. A valid receive symbol is at least 34 µs in duration. Any symbol cap-
tured on the bus between 8 µs and 34 µs in duration is considered invalid and is flagged by the
J_STAT register as a bus-symbol timing error.
receive symbol at that state. A valid receive symbol is at least 34 µs in duration. Any symbol cap-
tured on the bus between 8 µs and 34 µs in duration is considered invalid and is flagged by the
J_STAT register as a bus-symbol timing error.
8.3.2.3
Delay Compensation
Because the digital portion of the J1850 protocol is integrated onto the microcontroller and phys-
ically separated from the transceiver and J1850 bus, control over critical timing parameters of
various manufacturers’ remote transceivers is required. The delay compensation circuitry ad-
dresses this requirement by providing the flexibility to compensate for propagation delay and
pulse-width variations among various transceivers. The compensation circuitry synchronizes it-
self to the leading edge of each input symbol, which allows for accurate detection of bus conten-
tion during bit arbitration. The delay compensation is programmable through the J_DLY register
(Figure 8-18 on page 8-20).
ically separated from the transceiver and J1850 bus, control over critical timing parameters of
various manufacturers’ remote transceivers is required. The delay compensation circuitry ad-
dresses this requirement by providing the flexibility to compensate for propagation delay and
pulse-width variations among various transceivers. The compensation circuitry synchronizes it-
self to the leading edge of each input symbol, which allows for accurate detection of bus conten-
tion during bit arbitration. The delay compensation is programmable through the J_DLY register
(Figure 8-18 on page 8-20).
8.3.2.4
Symbol Encoding and Decoding
The J1850 protocol supports the Huntzicker encoding method, which is based on variable pulse-
width (VPW) bus modulation. VPW modulation is a forced high/low symbol transition formatting
scheme that tracks the duration between two consecutive transitions and the level of the bus, ac-
tive or passive (Figure 8-3).
width (VPW) bus modulation. VPW modulation is a forced high/low symbol transition formatting
scheme that tracks the duration between two consecutive transitions and the level of the bus, ac-
tive or passive (Figure 8-3).
Table 8-3. Relationships Between Input Frequency, PLL, and Prescaler Bits
F
XTAL
1
Internal Clock Frequency
(f/2)
PRE1
PRE0
PLL
Disabled
PLL
Enabled
8 MHz
4 MHz
4 MHz
0
0
12 MHz
6 MHz
6 MHz
0
1
16 MHz
8 MHz
8 MHz
1
0
20 MHz
10 MHz
10 MHz
1
1