Intel 8XC196Lx Manuale Utente

9-1

This chapter discusses the major hardware consideration differences between the 8XC196Lx and
the 8XC196Kx. The 8XC196Lx has implemented a reset source SFR that reveals the source of
the most recent reset request.

The reset source (RSTSRC) register indicates the source of the last reset that the microcontroller
encountered (Figure 9-1). If more than one reset occurs at the same time, all of the corresponding
RSTSRC bits are set. Reading this SFR clears all the register bits.

Address:

Reset State:

1F92H
XXH

(1)

The reset source (RSTSRC) register indicates the source(s) of the last reset that the microcontroller 
encountered.

—

—

—

—

CFDRST

WDTRST

SFWRST

EXTRST

7:4

—

Reserved; for compatibility with future devices, write zeros to these bits.

3

CFDRST

Clock Failure Detection Reset

When set, this bit indicates that a failed clock caused the last reset.

2

WDTRST

Watchdog Timer Reset

When set, this bit indicates that the watchdog timer caused the last reset.

1

SFWRST

Software Reset

When set, this bit indicates that either the RST instruction or the IDLPD 
instruction used with an illegal key caused the last reset.

0

EXTRST

External Reset

When set, this bit indicates that the RESET# pin being asserted caused the 
last reset.

NOTE:
1.

The State of the RSTSRC register is inderterminate on a V

CC

 power up condition. All other reset 

states will have the corresponding reset event bit set in the register.