Agilent Technologies 664xA Manuale Utente

 
 Meaning and Type
 Clear Status   Device Status
 
 Description
 This command causes the following actions (see "Chapter 4 - Status Reporting" for descriptions of all registers):

• 

Clears the following registers:

• 

Standard Event Status.

• 

Operation Status Event.

• 

Questionable Status Event.

• 

Status Byte.

• 

Clears the Error Queue.

• 

If *CLS immediately follows a program message terminator (<NL>), then the output queue and the MAV bit

are also cleared.

 
 

 

(None)

 

(None)

 
 Meaning and Type
 Event Status Enable    Device Status
 
 Description
 This command programs the Standard Event Status Enable register bits.  The programming determines which events of the
Standard Event Status Event register (see *ESR?) are allowed to set the ESB (Event Summary Bit) of the Status Byte
register.  A "1" in the bit position enables the corresponding event.  All of the enabled events of the Standard Event Status
Event register are logically ORed to cause the Event Summary Bit (ESB) of the Status Byte register to be set.  See "Chapter
4 - Status Reporting" for descriptions of all three registers.
 

 Bit Configuration of Standard Event Status Enable Register

 Bit Position

 7

 6

 5

 4

 3

 2

 1

 0

 Bit Name

 PON

 0

 CME

 EXE

 DDE

 QYE

 0

 OPC

 Bit Weight

 128

 64

 32

 16

 8

 4

 2

 1

 

 CME = Command error; DDE = Device-dependent error; EXE = Execution error;
OPC = Operation complete; PON Power-on; QYE = Query error.

 
 

 

 

(See *PSC)

 

(None)

 

 

 

 <NR1>      (Register value)

 

 

 If PSC is programmed to 0, then the *ESE command causes a write cycle to nonvolatile memory.  The
nonvolatile memory has a finite maximum number of write cycles (see Supplemental Characteristics in
Chapter 1 of the power supply Operating Guide).  Programs that repeatedly cause write cycles to non-

 

volatile memory can eventually  exceed the maximum number of write cycles and may cause the 
memory to fail.