Renesas R5S72644 Manuale Utente
Section 7 Interrupt Controller
Page 192 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the
interrupt source flag, "time from occurrence of interrupt request until interrupt controller
identifies priority, compares it with mask bits in SR, and sends interrupt request signal to
CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not
inadvertently accepted again, read the interrupt source flag after it has been cleared, and
then execute an RTE instruction.
identifies priority, compares it with mask bits in SR, and sends interrupt request signal to
CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not
inadvertently accepted again, read the interrupt source flag after it has been cleared, and
then execute an RTE instruction.
* Interrupt requests that are designated as edge-sensing are held pending until the
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ interrupt request register (IRQRR). For details, see section 7.4.3, IRQ
Interrupts.
Interrupts held pending due to edge-sensing are cleared by a power-on reset.
the IRQ interrupt request register (IRQRR). For details, see section 7.4.3, IRQ
Interrupts.
Interrupts held pending due to edge-sensing are cleared by a power-on reset.