Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Scheda Tecnica
Codici prodotto
P4X-UPE3210-316-6M1333
Datasheet
63
MCH Register Description
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any
device or bridge will result in a master abort.
device or bridge will result in a master abort.
4.5
I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
4.5.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
0CF8h Accessed as a DW
Default Value:
00000000h
Access:
R/W
Size:
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or
Word reference will "pass through" the Configuration Address Register and DMI onto
the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus
Number, Device Number, Function Number, and Register Number for which a
subsequent configuration access is intended.
Bit
Access &
Default
Description
31
R/W
0b
Configuration Enable (CFGE):
0 = Disable
0 = Enable.
0 = Disable
0 = Enable.
30:24
Reserved
23:16
R/W
00h
Bus Number: If the Bus Number is programmed to 00h the target of the
Configuration Cycle is a PCI Bus 0 agent. If this is the case and the MCH
is not the target (i.e., the device number is ≥ 2), then a DMI Type 0
Configuration Cycle is a PCI Bus 0 agent. If this is the case and the MCH
is not the target (i.e., the device number is ≥ 2), then a DMI Type 0
Configuration Cycle is generated.
If the Bus Number is non-zero and does not fall within the ranges
enumerated by device 1’s Secondary Bus Number or Subordinate Bus
Number Register, then a DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into
the Secondary Bus Number Register of device 1, a Type 0 PCI
configuration cycle will be generated on PCI Express.
If the Bus Number is non-zero, greater than the value in the Secondary
Bus Number register of device 1 and less than or equal to the value
programmed into the Subordinate Bus Number Register of device 1 a
Type 1 PCI configuration cycle will be generated on PCI Express.
This field is mapped to byte 8 [7:0] of the request header format during
PCI Express Configuration cycles and A[23:16] during the DMI Type 1
configuration cycles.
If the Bus Number is non-zero and does not fall within the ranges
enumerated by device 1’s Secondary Bus Number or Subordinate Bus
Number Register, then a DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into
the Secondary Bus Number Register of device 1, a Type 0 PCI
configuration cycle will be generated on PCI Express.
If the Bus Number is non-zero, greater than the value in the Secondary
Bus Number register of device 1 and less than or equal to the value
programmed into the Subordinate Bus Number Register of device 1 a
Type 1 PCI configuration cycle will be generated on PCI Express.
This field is mapped to byte 8 [7:0] of the request header format during
PCI Express Configuration cycles and A[23:16] during the DMI Type 1
configuration cycles.