Renesas R5S72646 Manuale Utente
Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00
Page 1589 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.12
Video Field Offset Register (VIDEO_FIELD_OFFSET)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VIDEO_FIELD_OFFSET[15:0]
VIDEO_FIELD_OFFSET[31:16]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 0 VIDEO_FIELD_
OFFSET
[31:0]
[31:0]
H'00000000 R/W
These bits specify the field offset. This setting is
valid in the video recording mode.
valid in the video recording mode.
The lower four bits should always be 0000.