Intel Xeon X3450 BX80605X3450 Manuale Utente

Intel® Xeon® Processor 3400 Series Datasheet, Volume 1

75

The PECI interface operates at a nominal voltage set by V

TT

. The set of DC electrical 

specifications shown in 

 is used with devices normally operating from a V

TT

 

interface supply. V

TT

 nominal levels will vary between processor families. All PECI 

devices will operate at the V

TT

 level determined by the processor installed in the 

system. For specific nominal V

TT

 levels, refer to 

.

1.

V

TT 

supplies the PECI interface. PECI behavior does not affect V

TT

 min/max specifications.

2.

The leakage specification applies to powered devices on the PECI bus.

The input buffers in both client and host models must use a Schmitt-triggered input 
design for improved noise immunity. Use 

 as a guide for input buffer design.

V

in

Input Voltage Range

-0.150

V

TT

 

V

V

hysteresis

Hysteresis

0.1 * V

TT

N/A

V

V

n

Negative-Edge Threshold Voltage

0.275 * V

TT

0.500 * V

TT

V

V

p

Positive-Edge Threshold Voltage

0.550 * V

TT

0.725 * V

TT

V

I

source

High-Level Output Source
(V

OH

 = 0.75 * V

TT

)

-6.0

N/A

mA

I

sink

Low-Level Output Sink
(V

OL

 = 0.25 * V

TT

)

0.5

1.0

mA

I

leak+

High Impedance State Leakage to 

V

TT

 (V

leak

 = V

OL

) 

N/A

100

µA

2

I

leak-

High Impedance Leakage to GND 

(V

leak

 = V

OH

)

N/A

100

µA

2

C

bus

Bus Capacitance per Node

N/A

10

pF

V

noise

Signal Noise Immunity above 

300 MHz

0.1 * V

TT

N/A

V

p-p

Minimum V

P

Maximum V

P

Minimum V

N

Maximum V

N

PECI High Range

PECI Low Range

Valid Input
Signal Range

Minimum
Hysteresis

V

TTD

PECI Ground