Zhone 7995 Guida Utente
A. Configuration Options
7990-A2-GB20-20
September 2004
A-11
Port (DTE) Initiated Loopbacks
Possible Settings: Disable, DTLB, DCLB, Both
Default Setting: Disable
Default Setting: Disable
Allows the initiation and termination of a local Data Terminal Loopback (DTLB) or remote
Data Channel Loopback (DCLB) by the DTE connected to this port. (DTLB is equivalent to
a V.54 loop 3, and DCLB is equivalent to a V.54 loop 2.) Control of these loopbacks is
through the DTE interchange circuits as specified by the V.54 standard.
Data Channel Loopback (DCLB) by the DTE connected to this port. (DTLB is equivalent to
a V.54 loop 3, and DCLB is equivalent to a V.54 loop 2.) Control of these loopbacks is
through the DTE interchange circuits as specified by the V.54 standard.
Disable – Disables control of local DTLBs and remote DCLBs by the DTE connected to
this port.
this port.
DTLB – Gives control of the local DTLBs for this port to the DTE attached to this port. This
loopback is controlled by the Local Loopback interchange circuit LL (CCITT 141).
loopback is controlled by the Local Loopback interchange circuit LL (CCITT 141).
DCLB – Gives control of the remote DCLBs for the far-end port connected to this port to
the DTE attached to this port. This loopback is controlled by the Remote Loopback
interchange circuit RL (CCITT 140). The far-end equipment must support in-band
V.54 loopbacks.
the DTE attached to this port. This loopback is controlled by the Remote Loopback
interchange circuit RL (CCITT 140). The far-end equipment must support in-band
V.54 loopbacks.
Both – Gives control of local DTLBs and remote DCLBs to the DTE connected to this
port.
port.
Elastic Store
Possible Settings: Disable, Enable
Default Setting: Enable
Default Setting: Enable
When configured as the STU-C and Transmit Clock Source is set to External, used to
enable or disable a first-in, first-out (FIFO) buffer circuit for the incoming external clock.
This circuit is used to compensate for the differences between the frequencies of the data
clocks for the two units in the circuit. Do not enable Elastic Store if the attached DCE has
an elastic store buffer larger than 32 bits.
enable or disable a first-in, first-out (FIFO) buffer circuit for the incoming external clock.
This circuit is used to compensate for the differences between the frequencies of the data
clocks for the two units in the circuit. Do not enable Elastic Store if the attached DCE has
an elastic store buffer larger than 32 bits.
Elastic Store appears only when DSL Mode is set to STU-C (see
) and the device is in Fixed Rate mode.
Disable – Disables the Elastic Store FIFO.
Enable – Enables the Elastic Store FIFO.
Table A-4.
Synchronous Data Port Options – Model 7995 (4 of 4)