Intel Xeon X3460 BX80605X3460 Manuale Utente
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BX80605X3460
Processor Integrated I/O (IIO) Configuration Registers
126
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.4.5.4
SR[12:15]—Scratch Pad Register 12-15 (Non-Sticky)
3.4.5.5
SR[16:17]—Scratch Pad Register 16-17 (Non-Sticky)
3.4.5.6
SR[18:23]—Scratch Pad Register 18-23 (Non-Sticky)
3.4.5.7
CWR[0:3]—Conditional Write Registers 0-3
Register:
SR[12:15]
Device:
8
Function: 1
Offset:
0ACh-0B8h by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Scratch Pad — Non-Sticky
Non-sticky scratch pad registers for firmware utilization.
Non-sticky scratch pad registers for firmware utilization.
Register:
SR[16:17]
Device:
8
Function: 1
Offset:
0BCh-0C0h by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Scratch Pad — Non-Sticky
Non-sticky scratch pad registers for firmware utilization.
Non-sticky scratch pad registers for firmware utilization.
Register:
SR[18:23]
Device:
8
Function: 1
Offset:
0C4h-0D8h by 4
Bit
Attr
Default
Description
31:0
RW
0h
Scratch Pad — Non-Sticky
Non-sticky scratch pad registers for firmware utilization.
Non-sticky scratch pad registers for firmware utilization.
Register:
CWR[0:3]
Device:
8
Function: 1
Offset:
0DCh-0E8h by 4
Bit
Attr
Default
Description
31:0
RWSLB
0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.