Intel Xeon X3460 BX80605X3460 Manuale Utente

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

295

 summarizes IIO behavior on inbound configuration transactions from any 

PCIe port.

1.

When forwarding Type 0 accesses to DMI, any device number in the configuration transaction is 

allowed/forwarded.

Type 0

N/A

Master Abort

Type 1

Inbound Configuration disabled 

Master Abort

Inbound Configuration enabled (by 
MISCCTRLSTS[1]) and bus 0

Master Abort

Inbound Configuration enabled and bus is 

between 1–255 and Bus number matches the 

internal bus number of IIO (IIOBUSNO or 

PBN register)

Master Abort

Inbound Configuration enabled and bus is 

between 1–255 and Bus number does not 

match the internal bus number of IIO 

(IIOBUSNO or PBN register) and bus number 

is outside of LCFGBUS.BASE/LCFGBUS.LIMIT 

and inside of 

GCFGBUS.BASE/GCFGBUS.LIMIT

Forward to Intel QuickPath Interconnect

Inbound Configuration enabled and bus is 

between 1–255 and Bus number does not 

match the internal bus number of IIO 

(IIOBUSNO or PBN register) and bus number 

is outside of 

GCFGBUS.BASE/GCFGBUS.LIMIT

Forward to subtractive decode port (DMI or 

Intel QuickPath Interconnect), if enabled 

using MISCCTRLSTS[1]

Inbound Configuration enabled and bus is 

between 1–255 and Bus number does not 

match the internal bus number of IIO 

(IIOBUSNO or PBN register) and is within 

LCFGBUS.BASE/LCFGBUS.LIMIT and one of 

the PCIe ports is positively decoded

Forward to that PCIe port.
Forward as Type 0/1 depending on secondary 

bus number of the port.

Inbound Configuration enabled and bus is 

between 1–255 and Bus number does not 

match the internal bus number of IIO 

(IIOBUSNO or PBN register) and is within 

LCFGBUS.BASE/LCFGBUS.LIMIT and none of 

the PCIe ports is positively decoded and DMI 

is the subtractive decode port

Forward to DMI
Forward as Type 0

1

/1 depending on 

secondary bus number of the port.

Inbound Configuration enabled and bus is 

between 1–255 and Bus number does not 

match the internal bus number of IIO 

(IIOBUSNO or PBN register) and is within 

LCFGBUS.BASE/LCFGBUS.LIMIT and none of 

the PCIe ports is positively decoded and DMI 

is not the subtractive decode port

Master Abort