Cisco Cisco ONS 15454 SONET Multiservice Provisioning Platform (MSPP) Guida Alla Risoluzione Dei Problemi

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Components Used
The information in this document is based on these software and hardware versions:
Cisco Router 7603 that runs Cisco IOS® Software Release 12.1(13)E13
• 
Cisco ONS 15454 that runs Cisco ONS Release 4.1.3
• 
ML (bundled as part of the ONS 4.1.3 release) that runs Cisco IOS Software Release 12.1(19)EO1
• 
The information in this document was created from the devices in a specific lab environment. All of the
devices used in this document started with a cleared (default) configuration. If your network is live, make sure
that you understand the potential impact of any command.
Conventions
Refer to Cisco Technical Tips Conventions for more information on document conventions.
Basic ML Architecture
The Cisco ML−Series cards for the ONS 15454 platform provide 10/100/1000 Mbps Ethernet connectivity
over SONET/SDH at layer 2 and layer 3. Each ML card in the chassis runs one independent IOS image.
Creation of a cross−connect circuit in Cisco Transport Controller (CTC) between ML ports creates virtual
backend Packet over SONET (POS) ports. In software releases 4.6 and later, creation of POS ports always
occurs, but the ports come up only when a cross−connect circuit creation occurs in CTC.
The ML1000−2 card has two POS ports (0 and 1). Each port has up to Synchronous Transport Signal
(STS)−24c bandwidth and a total of STS−48c per card. Each POS port supports subinterfaces to allow VLAN
trunking. Physical mapping of a POS port to an optical port occurs during the circuit creation phase, and can
change during optical span change. Thus, two POS ports on two ends of the circuit are peers, and their
configurations need to match.
The mapping between an Ethernet port and a POS port depends on the topology requirement. Layer 2
switching topology ties these two types of ports together with the same bridge−group number. Layer 3
topology routes packets between these interfaces.
Basic Test Topology
Figure 1 represents the test topology:
Figure 1  Test Topology