Cisco Cisco ASR 1000 Series 40Gbps SPA Interface Processor Scheda Tecnica
Data Sheet
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Additional Features of the SPA
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Unframed (unstructured) T1/E1 transport
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N x 64 kbps and N x 56 kbps framed T1 transport
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N x 64 kbps framed E1 transport
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Grooming of up to 84 (T1) or 63 (E1) separate data streams, each able to terminate on a
separate network destination
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BITS support
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Configurable clock source
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T1/E1 line diagnostic loopbacks (local line, local payload, and network payload)
Channelization Support
Circuit emulation:
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SONET (OC3): STS-3 -> STS-1 -> VTG -> VT1.5 -> DS1
DS0,
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SDH (STM-1): STM1 -> AU4 -> TUG-3 -> TUG-2 -> VC-12 -> E1
DS0
ATM:
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SONET (OC3): STS-3 -> STS-1 -> VTG -> VT1.5 -> DS1
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SDH (STM-1): STM1 -> AU4 -> TUG-3 -> TUG-2 -> VC-12 -> E1
Feature Details
Protocol-Independent Data Transport
These SPAs provide completely bit-transparent, bidirectional, point-to-point data transport. Every
bit presented to an ingress port is transported unchanged to the corresponding egress port by
encapsulating the data bits into a PWE packet for transport across an IP/MPLS network. The data
ports do not care about the structure or content of the data stream. Consequently, these SPAs are
ideally suited to transport data streams that are not suited to be carried using other platform
interfaces. Such data streams might include:
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Leased-line emulation services
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Encrypted data
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Data protocols that cannot easily be migrated to native IP, ATM, Frame Relay, HDLC, and
so on
Data Integrity
Because these SPAs do not consider the content of any circuit emulation data stream, it is
important to engineer the transport network in such a way as to minimize the risk of losing any
data packets.
To help ensure that a data stream is delivered, without gaps, to the destination CPE, data packets
are held in a dejitter buffer at the destination port to eliminate any delay variation (that is, jitter)
experienced by successive packets traveling through the network. The dejitter buffer is user
configurable up to 320 milliseconds (±160 milliseconds), depending upon the size of the payload
and the type of PWE being configured (nxDS0 or T1/E1, and so on).
Flexibility in Delay vs. Overhead