Cisco Cisco UCS C22 M3 Rack Server Scheda Tecnica

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Stateless Offloads and Performance Features  
(continued)
Features
Benefits
FCoE Transmit Segmentation Offloads
•  Enables the FCoE software to initiate a transmission of multiple FCoE packets up to a complete FC sequence with a single 
header in host memory (single instruction)
FCoE Coalescing and Direct Data Placement
• Hardware can provide DDP offload for up to 512 concurrent outstanding FC read or write exchanges
Traffic Class (TC) using 802.1p
• A specific TC can be configured to receive or transmit a specific amount of the total bandwidth available per port
Flow Director Filters: 
up to 32 KB - 2 Signature Filters 
up to 8 KB - 2 Perfect Match Filters
•  The flow director filters identify specific flows or sets of flows and routes them to specific queues These filters are an 
expansion of the L3/L4 5-tuple filters that provide up to additional 32 K filters
Support for packets up to 15.5KB (Jumbo Frames)
• Enables higher and better throughput of data
Low Latency Interrupts
•  Based on the sensitivity of the incoming data, the controller can bypass the automatic moderation of time intervals between 
the interrupts
Direct Cache Access (DCA) support
• Method to improve network I/O performance by placing some posted inbound writes directly within CPU cache
TCP Timer Interrupts
• Enables the software driver to read a EICR register bit set by the controller, avoiding cache thrash and enabling parallelism
No Snoop
•  System logic can provide a separate path into system memory for non-coherent traffic. The non-coherent path to system 
memory provides a higher, more uniform, bandwidth for write requests
Relax Ordering
•  When the strict
 
order of packets is not required, the device can send packets in an order that allows for less power consumption 
and greater CPU efficiency
Rx Packet Split Header 
• Helps the driver to focus on the relevant part of the packet without the need to parse
Descriptor ring management hardware for Transmit and Receive
• Optimized descriptor fetch and write-back for efficient system memory and PCIe bandwidth usage
Remote Boot Options
Features
Benefits
Preboot eXecution Environment (PXE) flash interface support
• Enables system boot up via the EFI (32 bit and 64 bit)
• Flash interface for PXE 2.1 option ROM
Intel® Ethernet FCoE Boot 
• Enables system boot up via FCoE
Intel® Ethernet iSCSI Remote Boot
• Enables system boot up via iSCSI
Intel Boot Agent software: Linux boot via PXE or 
BOOTP,Windows* Deployment Services, or UEFI
• Allows networked computer to boot using a program code image supplied by a remote server
• Complies with the Pre-boot eXecution Environment (PXE) Version 2.1 Specification
Manageability Features
Features
Benefits
DMTF Network Controller Sideband Interface (NC-SI) 
Pass-through
• Supports pass through traffic between BMC and Controller’s LAN functions
Advanced Pass Through (APT)
• Compatible Management Packet Transmit/Receive Support
Manageability and Host Packet Filtering
• Packets that pass the MAC address filters and VLAN address filters are routed to either the Host or a Management Controller
Intel® System Management Bus (SMBus) Pass-through
• Enables BMC to configure the Controller’s filters and management related capabilities
Management Component Transport Protocol (MCTP)
• Baseboard management controller (BMC) communication between add-in devices within the platform
Host-Based Application-to-BMC Network Communication Patch 
(OS2BMC)
•  Filtering method that enables server management software to communicate with a management controller via standard 
networking protocols such as TCP/IP instead of a chipset-specific interface
Private OS2BMC Traffic Flow
• BMC may have its own private connection to the network controller and network flows are blocked
DMTF MCTP Protocol Over SMBus
• Enables reporting and controlling information via NC-SI using the MCTP protocol over SMBus
Firmware Based Thermal Management
• Can be programmed via the BMC to initiate thermal actions and report thermal occurrences
IEEE 802.3 Management Data Input/Output Interface (MDIO 
Interface or MII Management Interface)
• Enables the MAC and software to monitor and control the state of the PHY
MAC/PHY Control and Status
• Enhanced control capabilities through PHY reset, link status, duplex indication, and MAC Dx power state
Watchdog timer
• The MAC and each PHY supports a watchdog timer to detect a stuck microcontroller
Advanced Error Reporting (AER)
• Messaging support to communicate multiple types/severity of errors
Controller Memory Integrity Protection
• Main internal memories are protected by error correcting code (ECC) or parity bits
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