Intel Xeon 7130N LF80550KF0878M Scheda Tecnica
Codici prodotto
LF80550KF0878M
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
73
7
Features
7.1
Power-On Configuration Options
Several configuration options can be set by hardware. The Dual-Core Intel Xeon processor 7000
series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#.
For specifications on these options, refer to
series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#.
For specifications on these options, refer to
The sampled information configures the processor for subsequent operation. These configuration
options can only be changed by another reset. All resets configure the processor. For most reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
options can only be changed by another reset. All resets configure the processor. For most reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
7.2
Clock Control and Low Power States
The processor allows the use of HALT and Stop-Grant states to reduce power consumption by
stopping the clock to internal sections of the processor, depending on each particular state. The
Dual-Core Intel Xeon processor 7000 series also adds support for the Enhanced HALT state. For
more configuration details also refer to the Prescott, Nocona and Potomac Processor BIOS
Writer’s Guide.See
stopping the clock to internal sections of the processor, depending on each particular state. The
Dual-Core Intel Xeon processor 7000 series also adds support for the Enhanced HALT state. For
more configuration details also refer to the Prescott, Nocona and Potomac Processor BIOS
Writer’s Guide.See
for a visual representation of the processor low power states.
7.2.1
Normal State
This is the normal operating state for the processor.
Table 7-1. Power-On Configuration Option Pins
Configuration Option
Pin
Notes
Output tri state
SMI#
1,
2
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
Execute BIST (Built-In Self Test)
INIT#
In Order Queue de-pipelining (set IOQ depth to 1)
A7#
Disable MCERR# observation
A9#
Disable BINIT# observation
A10#
Disable bus parking
A15#
APIC Cluster ID
A[12:11]#
Symmetric agent arbitration ID
BR[3:0]#
Disable Hyper-Threading Technology
A31#
3
3. This mode is not tested.