Intel D525 AU80610006225AA Manuale Utente
Codici prodotto
AU80610006225AA
Low Power Features
54
Datasheet
6
Low Power Features
This chapter provides information on power management topics.
6.1
Low Power States
The low states supported by the processor are described in this section.
6.1.1
Processor Core Low Power States
When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-states. However,
higher C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor core package level. Thread level C-states are
available if Hyper-Threading Technology is enabled.
power. More power savings actions are taken for numerically higher C-states. However,
higher C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor core package level. Thread level C-states are
available if Hyper-Threading Technology is enabled.
6.1.1.1
Clock Control and Low-Power States
The processor core supports low power states at the thread level and core/package
level. Thread states (TCx) loosely correspond to ACPI processor core power states (Cx).
A thread may independently enter TC1/AutoHALT, TC1/MWAIT but this does not always
cause a power state transition. Only when both threads request a low-power state
(TCx) greater than the current processor core state will a transition occur. The central
power management logic ensures the entire processor core enters the new common
processor core power state. Package states are states that require external
intervention and typically map back to processor core power states. Package states for
processor core include Normal (C0, C1) states.
level. Thread states (TCx) loosely correspond to ACPI processor core power states (Cx).
A thread may independently enter TC1/AutoHALT, TC1/MWAIT but this does not always
cause a power state transition. Only when both threads request a low-power state
(TCx) greater than the current processor core state will a transition occur. The central
power management logic ensures the entire processor core enters the new common
processor core power state. Package states are states that require external
intervention and typically map back to processor core power states. Package states for
processor core include Normal (C0, C1) states.
Table 6-42.System States
State
Description
G0/S0
Full On
G2/S5
Soft off. All power lost (except wakeup on Intel NM10 Express Chipset). Total
reboot. (swh - I changed to ecpd_2#)
reboot. (swh - I changed to ecpd_2#)
G3
Mechanical/hard off. All power (AC and battery) (AC and battery) removed
from system.
from system.
Table 6-43.Processor Core Idle States
State
Description
C0
Active mode, processor executing code.
C1
AutoHALT state.