Intel Itanium 9140M NE80567KF028009 Manuale Utente
Codici prodotto
NE80567KF028009
12
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
Introduction
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel
®
Itanium
®
Processor Family
System Abstraction Layer Specification.
1.3
Mixing Processors of Different Frequencies and
Cache Sizes
All Dual-Core Intel Itanium processor 9000 and 9100 series on the same system bus
are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and
identical core frequency. Mixing components of different core frequencies and cache
sizes is not supported and has not been validated by Intel. Operating system support
for multiprocessing with mixed components should also be considered.
are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and
identical core frequency. Mixing components of different core frequencies and cache
sizes is not supported and has not been validated by Intel. Operating system support
for multiprocessing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multiprocessor
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
1.4
Terminology
In this document, “the processor” refers to the “Dual-Core Intel Itanium processor
9000 and 9100 series” processor, unless otherwise indicated.
9000 and 9100 series” processor, unless otherwise indicated.
A ‘#’ symbol after a signal name refers to an active low signal. This means that a signal
is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is
high, a non-maskable interrupt has occurred. In the case of lines where the name does
not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’
refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H = High logic level,
L = Low logic level).
is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is
high, a non-maskable interrupt has occurred. In the case of lines where the name does
not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’
refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H = High logic level,
L = Low logic level).
The term “system bus” refers to the interface between the processor, system core logic,
and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O.
and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O.
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain
subscript, for example, V
subscript, for example, V
core
, or a capitalized, abbreviated subscript, for example, T
CO
.
1.5
State of Data
The data contained in this document is subject to change. It is the best information
that Intel is able to provide at the publication date of this document.
that Intel is able to provide at the publication date of this document.