Intel Itanium 9140M NE80567KF028009 Manuale Utente

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Also available on the SMBus interface on the processor is an EEPROM which may be 
used for other data at the system vendor’s discretion (Intel will not be using the scratch 
EEPROM). The data in this EEPROM, once programmed, can be write-protected by 
asserting the active-high SMWP signal. This signal has a weak pull-down (10 kΩ) to 

allow the EEPROM to be programmed in systems with no implementation of this signal.

The processor information ROM and scratch EEPROM responds to three of the SMBus 
packet types: current address read, random address read, and sequential read.

 shows the format of the current address read SMBus packet. The internal 

address counter keeps track of the address accessed during the last read or write 
operation, incremented by one. Address “roll over” during reads is from the last byte of 
the last eight byte page to the first byte of the first page. “Roll over” during writes is 
from the last byte of the current eight byte page to the first byte of the same page. 

 shows the format of the random read SMBus packet. The write with no data 

loads the address desired to be read. Sequential reads may begin with a current 
address read or a random address read. After the SMBus host controller receives the 
data word, it responds with an acknowledge. This will continue until the SMBus host 
controller responds with a negative acknowledge and a stop. 

 shows the format of the byte write SMBus packet. The page write operates 

the same way as the byte write, except that the SMBus host controller does not send a 
stop after the first data byte and acknowledge. The Scratch EEPROM internally 
increments its address. The SMBus host controller continues to transmit data bytes 
until it terminates the sequence with a stop. All data bytes will result in an acknowledge 
from the Scratch EEPROM. If more than eight bytes are written, the internal address 
will “roll over” and the previous data will be overwritten. 

In 

bit, ‘R’ represents a read, ‘W’ represents a write bit, ‘A’ represents an acknowledge, and 
‘///’ represents a negative acknowledge. The shaded bits are transmitted by the 
processor information ROM or Scratch EEPROM and the bits that are not shaded are 
transmitted by the SMBus host controller. In the tables, the data addresses indicate 
eight bits. The SMBus host controller should transmit eight bits, but as there are only 
128 addresses, the most significant bit is a don’t care.

1. Refer to the Intel® Itanium™ Architecture Software Developer’s Manual for details on CPUID registers.

2. The translation is using BCD.

3. Itanium 9000 and 9100 series use a hex-to-decimal conversion

1

7  bits

1

1

8 bits

1

1