Intel D425 AU80610006252AA Manuale Utente

Datasheet 

 33 

0 RO  0b Core 

I/O Access Enable (IOAE):  
 This bit is not implemented in the CPU 
Uncore and is hardwired to a 0. Writes to 
this bit position have no effect. 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

6-7h 

Default Value: 

0090h 

Access: 

 RWC; RO; 

Size: 16 

bits 

 This status register reports the occurrence of error events on Device 0's PCI 
interface. Since the CPU Uncore Device 0 does not physically reside on PCI_A many of 

the bits are not implemented. 

15 RWC  0b  Core 

Detected Parity Error (DPE):  
This bit is set when this Device receives a 
Poisoned TLP. 

14 RWC  0b  Core 

Signaled System Error (SSE):  
 This bit is set to 1 when the CPU Uncore Device 
0 generates an SERR message over DMI for any 
enabled Device 0 error condition. Device 0 error 
conditions are enabled in the PCICMD, 
ERRCMD, and DMIUEMSK registers. Device 0 
error flags are read/reset from the PCISTS, 
ERRSTS, or DMIUEST registers. Software clears 
this bit by writing a 1 to it. 

13 RWC  0b  Core 

Received Master Abort Status (RMAS):  
 This bit is set when the CPU Uncore generates 
a DMI request that receives an Unsupported 
Request completion packet. Software clears this 
bit by writing a 1 to it. 

12 RWC  0b  Core 

Received Target Abort Status (RTAS):  
 This bit is set when the CPU Uncore generates 
a DMI request that receives a Completer Abort 
completion packet. Software clears this bit by 
writing a 1 to it. 

11 RO  0b Core 

Signaled Target Abort Status (STAS):  
 The CPU Uncore will not generate a Target 
Abort DMI completion packet or Special Cycle. 
This bit is not implemented in the CPU Uncore 
and is hardwired to a 0. Writes to this bit 
position have no effect.