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Intel
D425
Manuale Utente
Intel D425 AU80610006252AA Manuale Utente
Codici prodotto
AU80610006252AA
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Schermo intero
Standard
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4
Datasheet
1.5.33
BGSM - Base of GTT stolen Memory ........................................... 58
1.5.34
TSEGMB - TSEG Memory Base ................................................... 59
1.5.35
TOLUD - Top of Low Usable DRAM ............................................. 59
1.5.36
ERRSTS - Error Status ............................................................. 61
1.5.37
ERRCMD - Error Command ....................................................... 62
1.5.38
SMICMD - SMI Command ......................................................... 63
1.5.39
SKPD - Scratchpad Data ........................................................... 64
1.5.40
CAPID0 - Capability Identifier .................................................... 64
1.6
MCHBAR ............................................................................................. 66
1.6.1
CHDECMISC - Channel Decode Misc ........................................... 67
1.6.2
C0DRB0 - Channel 0 DRAM Rank Boundary Address 0 .................. 68
1.6.3
C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................. 69
1.6.4
C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................. 69
1.6.5
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................. 70
1.6.6
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ........................... 70
1.6.7
C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute .......................... 72
1.6.8
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ................................ 72
1.6.9
C0CYCTRKACT - Channel 0 CYCTRK ACT ..................................... 73
1.6.10
C0CYCTRKWR - Channel 0 CYCTRK WR....................................... 74
1.6.11
C0CYCTRKRD - Channel 0 CYCTRK READ .................................... 75
1.6.12
C0CYCTRKREFR - Channel 0 CYCTRK REFR .................................. 76
1.6.13
C0CKECTRL - Channel 0 CKE Control .......................................... 76
1.6.14
C0REFRCTRL - Channel 0 DRAM Refresh Control .......................... 78
1.6.15
C0ODTCTRL - Channel 0 ODT Control ......................................... 80
1.6.16
PMSTS - Power Management Status ........................................... 81
1.7
DMIBAR .............................................................................................. 82
1.7.1
DMIVCECH - DMI Virtual Channel Enhanced Capability .................. 83
1.7.2
DMIPVCCAP1 - DMI Port VC Capability Register 1 ......................... 84
1.7.3
DMIPVCCAP2 - DMI Port VC Capability Register 2 ......................... 85
1.7.4
DMIPVCCTL - DMI Port VC Control ............................................. 85
1.7.5
DMIVC0RCAP - DMI VC0 Resource Capability ............................... 86
1.7.6
DMIVC0RCTL0 - DMI VC0 Resource Control ................................. 86
1.7.7
DMIVC0RSTS - DMI VC0 Resource Status ................................... 87
1.7.8
DMIVC1RCAP - DMI VC1 Resource Capability ............................... 88
1.7.9
DMIVC1RCTL1 - DMI VC1 Resource Control ................................. 89
1.7.10
DMIVC1RSTS - DMI VC1 Resource Status ................................... 90
1.7.11
DMIRCLDECH - DMI Root Complex Link Declaration ...................... 91
1.7.12
DMIESD - DMI Element Self Description ...................................... 91
1.7.13
DMILE1D - DMI Link Entry 1 Description ..................................... 92
1.7.14
DMILE1A - DMI Link Entry 1 Address .......................................... 93
1.7.15
DMILE2D - DMI Link Entry 2 Description ..................................... 94
1.7.16
DMILE2A - DMI Link Entry 2 Address .......................................... 95
1.7.17
DMIRCILCECH - DMI Root Complex Internal Link Control .............. 95
1.7.18
DMILCAP - DMI Link Capabilities ................................................ 96
1.7.19
DMILCTL - DMI Link Control ...................................................... 97
1.7.20
DMILSTS - DMI Link Status ....................................................... 98
1.8
EPBAR ................................................................................................ 98
1.8.1
EPESD - EP Element Self Description .......................................... 99
1.8.2
EPLE1D - EP Link Entry 1 Description ....................................... 100
1.8.3
EPLE1A - EP Link Entry 1 Address ............................................ 101
1.8.4
EPLE2D - EP Link Entry 2 Description ....................................... 101
1.8.5
EPLE2A - EP Link Entry 2 Address ............................................ 102
1.9
PCI Device 2 Function 0 ...................................................................... 102
1.9.1
VID2 - Vendor Identification ................................................... 105
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