Intel D425 AU80610006252AA Manuale Utente

58  

Datasheet  

31:20 RW/L  000h  Core 

Graphics Base of Stolen Memory (GBSM):  
This register contains bits 31 to 20 of the base 
address of stolen DRAM memory. BIOS 
determines the base of graphics stolen memory 
by subtracting the graphics stolen memory size 
(PCI Device 0 offset 52 bits 6:4) from TOLUD 
(PCI Device 0 offset B0 bits 15:04). 

NOTE:  This register is locked and becomes 

Read Only when the D_LCK bit in the 
SMRAM register is set.  

 

19:0 RO 00000h 

Core 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

A8-ABh 

Default Value: 

00000000h 

Access: 

 RO; RW/L; 

Size: 32 

bits 

This register contains the base address of stolen DRAM memory for the GTT. BIOS 
determines the base of GTT stolen memory by subtracting the GTT graphics stolen 

memory size (PCI Device 0 offset 52 bits 9:8) from the graphics stolen memory base 

(PCI Device 0 offset A4 bits 31:20).  

Note:  This register is locked and becomes Read Only when the D_LCK bit in the SMRAM 

register is set.   

 

 

31:20 RW/L  000h  Core 

Graphics Base of Stolen Memory (GBSM):  
This register contains bits 31 to 20 of the base 
address of stolen DRAM memory. BIOS 
determines the base of graphics stolen memory 
by subtracting the GTT graphics stolen memory 
size (PCI Device 0 offset 52 bits 9:8) from the 
graphics stolen memory base (PCI Device 0 
offset A4 bits 31:20). 

NOTE:  This register is locked and becomes 

Read Only when the D_LCK bit in the 
SMRAM register is set.   

19:0 RO 00000h 

Core