Intel D425 AU80610006252AA Manuale Utente
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AU80610006252AA
Processor Configuration Registers
Datasheet
87
Bit Access Default
Value
RST/P
WR
Description
23:20 RO
0h Core
Reserved ():
19:17 RW 000b Core
Port Arbitration Select (PAS):
Configures the VC resource to provide a
particular Port Arbitration service. Valid value for
this field is a number corresponding to one of
the asserted bits in the Port Arbitration
Capability field of the VC resource. Because only
bit 0 of that field is asserted. This field will
Configures the VC resource to provide a
particular Port Arbitration service. Valid value for
this field is a number corresponding to one of
the asserted bits in the Port Arbitration
Capability field of the VC resource. Because only
bit 0 of that field is asserted. This field will
always be programmed to '1'.
16:8 RO 000h Core
Reserved ()
7:1 RW 7Fh Core
Traffic Class / Virtual Channel 0 Map
(TCVC0M):
Indicates the TCs (Traffic Classes) that are
mapped to the VC resource. Bit locations within
this field correspond to TC values. For
(TCVC0M):
Indicates the TCs (Traffic Classes) that are
mapped to the VC resource. Bit locations within
this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is
mapped to this VC resource. When more than
one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the
TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
mapped to this VC resource. When more than
one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the
TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
0 RO 1b Core
Traffic Class 0 / Virtual Channel 0 Map
(TC0VC0M):
Traffic Class 0 is always routed to VC0.
(TC0VC0M):
Traffic Class 0 is always routed to VC0.
1.7.7
DMIVC0RSTS - DMI VC0 Resource Status
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
1A-1Bh
Default Value:
0002h
Access:
RO;
Size: 16
bits
Reports the Virtual Channel specific status.
Bit Access Default
Value
RST/
PWR
Description
15:2 RO 0000h Core
Reserved ():
Reserved and Zero for future R/WC/S
implementations. Software must use 0 for
writes to these bits.
Reserved and Zero for future R/WC/S
implementations. Software must use 0 for
writes to these bits.
1 RO 1b Core
Virtual Channel 0 Negotiation Pending
(VC0NP):
0: The VC negotiation is complete.
1: The VC resource is still in the process of
negotiation (initialization or disabling). This bit
(VC0NP):
0: The VC negotiation is complete.
1: The VC resource is still in the process of
negotiation (initialization or disabling). This bit
indicates the status of the process of Flow