Intel D425 AU80610006252AA Manuale Utente
Codici prodotto
AU80610006252AA
Processor Configuration Registers
106
Datasheet
1.9.3
PCICMD2 - PCI Command
B/D/F/Type: 0/2/0/PCI
Address Offset:
4-5h
Default Value:
0000h
Access:
RO; RW;
Size: 16
bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit Access Default
Value
Description
15:11 RO
00h
Reserved ():
10 RW 0b
Interrupt Disable (INTDIS):
This bit disables the device from asserting INTx#.
0: Enable the assertion of this device's INTx# signal.
1: Disable the assertion of this device's INTx# signal.
DO_INTx messages will not be sent to DMI.
This bit disables the device from asserting INTx#.
0: Enable the assertion of this device's INTx# signal.
1: Disable the assertion of this device's INTx# signal.
DO_INTx messages will not be sent to DMI.
9 RO 0b
Fast Back-to-Back (FB2B):
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
8 RO 0b
SERR Enable (SERRE):
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
7 RO 0b
Address/Data Stepping Enable (ADSTEP):
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
6 RO 0b
Parity Error Enable (PERRE):
Not Implemented. Hardwired to 0. Since the IGD
belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues
with normal operation.
Not Implemented. Hardwired to 0. Since the IGD
belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues
with normal operation.
5 RO 0b
Video Palette Snooping (VPS):
This bit is hardwired to 0 to disable snooping.
This bit is hardwired to 0 to disable snooping.
4 RO 0b
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write
and invalidate commands.
Hardwired to 0. The IGD does not support memory write
and invalidate commands.
3 RO 0b
Special Cycle Enable (SCE):
This bit is hardwired to 0. The IGD ignores Special cycles.
This bit is hardwired to 0. The IGD ignores Special cycles.
2 RW 0b
Bus Master Enable (BME):
This bit controls the IGD's response to bus master
accesses.
0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI compliant
master.
This bit controls the IGD's response to bus master
accesses.
0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI compliant
master.