Intel L7555 AT80604004875AA Manuale Utente
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AT80604004875AA
Intel® Xeon® Processor 7500 Datasheet, Volume 1
23
Electrical Specifications
2.4
Processor DC Specifications
Voltage and current specifications are detailed in
. For platform planning refer
to
, which provides Vcc static and transient tolerances.
Differential SYSCLK specifications are found in
. Control Sideband and Test
Access Port (TAP) are listed in
list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (T
CASE
as specified in
), clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
Power Up, RESETs
Single ended
CMOS Input
PWRGOOD, VIOPWRGOOD,
Single ended
GTL Input
RUNBIST, RESET_N
Thermal
Single ended
GTL Input
Force_PR_N
Single ended
GTL
MEM_Throttle[1]_N,MEM_Throttle[0]_N
Single ended
GTL-Open Drain
PROCHOT_N, THERMTRIP_N
Single ended
CMOS - Open Drain
Thermalert_N
VID
Single ended
CMOS Output
VID[7:0], CVID[7:1]
Single ended
Open/Ground
VIO_VID[4:1]
Voltage, and Voltage Regulator
Differential
Power
ISENSE_DN, ISENSE_DP
Single ended
Power
Vcc, VREG, VCACHE, VCACHESENSE,
VCC33,VCORESENSE, VIO, PSI_CACHE_N,PSI_N,
VSSCACHESENSE,VSSCORESENSE,
Debug
Single ended
GTL I/O-OD
MBP[7:0]_N, PRDY_N,PREQ_N
Notes:
1.
See
for signal descriptions.
Table 2-4.
Signals with R
TT
Signals with RTT
• QPI[3:0]R[P/N]Dat[19:0], QPI[5:4]R[P/N]CLK0, QPI[3:0]T[P/N]Dat[19:0],
QPI[5:4]T[P/N]CLK0
• FBD0NBICLK[A/B][P/N]0, FBD1NBICLK[C/D][P/N]0, FBD0SBOCLK[A/B][P/N]0,
FBD1SBOCLK[C/D][P/N]0, FBD0NBI[A/B][P/N][12:0], FBD1NBI[C/D][P/
N][12:0], FBD0SBO[A/B][P/N][9:0], FBD1SBO[C/D][P/N][9:0].
Table 2-3.
Signal Groups (Sheet 2 of 2)
Signal Group
Type
Signals
1