Intel Xeon L3406 CM80616005010AA Manuale Utente
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CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
50
Datasheet, Volume 2
3.3.3.27
BCTRL—Bridge Control Register
The Bridge Control register provides additional control for the secondary interface (that
is, PCI Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-to-PCI bridge embedded within the Integrated I/O, for example, VGA-compatible
address range mapping.
is, PCI Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-to-PCI bridge embedded within the Integrated I/O, for example, VGA-compatible
address range mapping.
(Sheet 1 of 2)
Register:
BCTRL
Device: 3-6
(PCIe)
Function:
0
Offset:
3Eh
Bit
Attr
Default
Description
15:12
RO
0h
Reserved
11
RO
0
Discard Timer SERR Status
Not applicable to PCI Express*. This bit is hardwired to 0.
Not applicable to PCI Express*. This bit is hardwired to 0.
10
RO
0
Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
9
RO
0
Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
8
RO
0
Primary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
7
RO
0
Fast Back-to-Back Enable
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
6
RW
0
Secondary Bus Reset
0 = No reset happens on the PCI Express port.
0 = No reset happens on the PCI Express port.
1 = Setting this bit triggers a hot reset on the link for the corresponding PCI
Express port and the PCI Express hierarchy domain subordinate to the
port. This sends the LTSSM into the Training (or Link) Control Reset state,
which necessarily implies a reset to the downstream device and all
subordinate devices. The transaction layer corresponding to port will be
emptied by Integrated I/O when this bit is set. This means that in the
outbound direction, all posted transactions are dropped and non-posted
transactions are sent a UR response. In the inbound direction,
completions for inbound NP requests are dropped when they arrive.
Inbound posted writes are required to be flushed as well either by
dropping the packets are by retiring them normally.
Note also that a secondary bus reset will not reset the virtual PCI-to-PCI
bridge configuration registers of the targeted PCI Express port.
5
RO
0
Master Abort Mode
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
4
RW
0
VGA 16-bit Decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses every 1 KB.
0 = Execute 10-bit address decodes on VGA I/O accesses.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
This bit only has meaning if bit 3 of this register is also set to 1, enabling VGA
This bit only has meaning if bit 3 of this register is also set to 1, enabling VGA
I/O decoding and forwarding by the bridge.
Refer to the PCI-to-PCI Bridge Specification for further details of this bit
Refer to the PCI-to-PCI Bridge Specification for further details of this bit
behavior.
3
RW
0
VGA Enable
This bit controls the routing of processor initiated transactions targeting VGA
This bit controls the routing of processor initiated transactions targeting VGA
compatible I/O and memory address ranges. This bit must only be set for one
PCI Express port.