Intel 2 Duo T7250 LE80537GG0412M Manuale Utente
Codici prodotto
LE80537GG0412M
Low Power Features
12
Datasheet
Figure 1.
Core Low Power States
C2
†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3
†
Core
state
state
break
P_LVL3 or
MWAIT(C3)
C1/
MWAIT
Core state
break
MWAIT(C1)
C1/Auto
Halt
Halt break
HLT instruction
C4
† ‡
Core State
break
P_LVL4 or
P_LVL5
ø
or
MWAIT(C4)
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state
.
Ø — P_LVL5 read is issued once the L2 cache is reduced to zero.