Intel 7140N LF80550KF093007 Scheda Tecnica
Codici prodotto
LF80550KF093007
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
5
Stop Clock State Machine ................................................................................... 85
Recommended Processor Layout and Pitch.......................................................... 124
Tables
Voltage Identification (VID) Definition .................................................................. 22
Cache Voltage Identification (CVID) Definition....................................................... 23
2-10 Voltage and Current Specifications....................................................................... 28
2-11 VCC Static and Transient Tolerance ..................................................................... 31
2-12 VCACHE Static and Transient Tolerance at the Die Sense Location ........................... 33
2-13 VCACHE Static and Transient Tolerance at the Board.............................................. 34
2-14 VCC Overshoot Specification ............................................................................... 35
2-15 VCACHE Overshoot Specification ......................................................................... 35
2-16 Front Side Bus Differential BCLK Specifications ...................................................... 36
2-17 BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications .......................................... 37
2-18 VIDPWRGD DC Specifications.............................................................................. 37
2-19 AGTL+ Signal Group DC Specifications ................................................................. 38
2-20 PWRGOOD and TAP Signal Group DC Specifications................................................ 38
2-21 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
2-11 VCC Static and Transient Tolerance ..................................................................... 31
2-12 VCACHE Static and Transient Tolerance at the Die Sense Location ........................... 33
2-13 VCACHE Static and Transient Tolerance at the Board.............................................. 34
2-14 VCC Overshoot Specification ............................................................................... 35
2-15 VCACHE Overshoot Specification ......................................................................... 35
2-16 Front Side Bus Differential BCLK Specifications ...................................................... 36
2-17 BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications .......................................... 37
2-18 VIDPWRGD DC Specifications.............................................................................. 37
2-19 AGTL+ Signal Group DC Specifications ................................................................. 38
2-20 PWRGOOD and TAP Signal Group DC Specifications................................................ 38
2-21 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group