Intel 7140N LF80550KF093007 Scheda Tecnica
Codici prodotto
LF80550KF093007
Features
88
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Note:
Actual implementation may vary. This figure is provided to offer a general understanding of the
architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
7.4.1
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors
on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the
the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors
on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes one of three upper address patterns from the
bus of the form “0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing,
as implemented, uses the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state.
Therefore, the thermal sensor supports nine unique addresses. To set either pin for the
Hi-Z state, the pin must be left floating. As before, the “Z” bit is the read/write bit for
the serial transaction.
bus of the form “0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing,
as implemented, uses the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state.
Therefore, the thermal sensor supports nine unique addresses. To set either pin for the
Hi-Z state, the pin must be left floating. As before, the “Z” bit is the read/write bit for
the serial transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be
generated by an SMBus master. The thermal sensor samples and latches the
SM_TS_A[1:0] signals at power-up. System designers should ensure that these signals
are at valid V
generated by an SMBus master. The thermal sensor samples and latches the
SM_TS_A[1:0] signals at power-up. System designers should ensure that these signals
are at valid V
IH
, V
IL
, or floating input levels prior to or while the thermal sensor’s
SM_VCC supply powers up. This should be done by pulling the pins to SM_VCC or V
SS
Figure 7-2. Logical Schematic of SMBus Circuitry