Intel T3500 AW80577GG0451ML Manuale Utente

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AW80577GG0451ML
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Intel
®
 Celeron
®
 Processor on 0.13 Micron Process in the 478-Pin Package
 Datasheet
System Bus Signal Quality Specifications
Figure 24. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD 
and TAP Buffers
0.5 * Vcc
Vt+ (min)
Vt+ (max)
Vt- (max)
Vcc
Allowable Ringback
Vss
Threshold Region to switch
receiver to a logic 1.
Figure 25. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD 
and TAP Buffers
0.5 * Vcc
Vt+ (min)
Vt- (max)
Vcc
Vss
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Allowable Ringback