Intel LF80550KG0888M Scheda Tecnica
Electrical Specifications
24
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
silicon. Most unused AGTL+ inputs may be left as no-connects since AGTL+ termination
is provided on the processor silicon. See
is provided on the processor silicon. See
for details on AGTL+ signals that do
not include on-die termination. Unused active-high inputs should be connected through
a resistor to ground (V
a resistor to ground (V
SS
). Unused outputs may be left unconnected. However, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TT
). See
Table 2-15
.
Most TAP signals, GTL+ asynchronous inputs, and GTL+ asynchronous outputs do not
include on-die termination (see
include on-die termination (see
for those signals which do not have on-die
termination). Inputs and used outputs must be terminated on the system board.
Unused outputs may be terminated on the system board or left connected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guide and the
appropriate debug port design guide.
Unused outputs may be terminated on the system board or left connected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guide and the
appropriate debug port design guide.
Don’t Care pins are pins on the processor package that are not connected to the
processor die. These pins can be connected on the motherboard in any way necessary
for compatible motherboard designs to support other processor versions.
processor die. These pins can be connected on the motherboard in any way necessary
for compatible motherboard designs to support other processor versions.
The TESTHI pins should be tied to V
TT
using a matched resistor, where a matched
resistor has a resistance value within +/-20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as
detailed below. Please note that utilization of boundary scan test will not be functional if
pins are connected together. A matched resistor should be used for each group:
detailed below. Please note that utilization of boundary scan test will not be functional if
pins are connected together. A matched resistor should be used for each group:
• TESTHI[3:0]
• TESTHI[6:5]
• TESTHI4 --- cannot be grouped with other TESTHI signals
• TESTHI[6:5]
• TESTHI4 --- cannot be grouped with other TESTHI signals
2.5
Mixing Processors
Intel supports and validates multi-processor configurations in which all processors
operate with the same front side bus frequency, core frequency and internal cache
sizes. Mixing processors operating at different internal clock frequencies is not
supported and will not be validated by Intel. Intel does not support or validate
operation of processors with different cache sizes. Mixing different processor steppings
but the same model (as per the CPUID instruction) is supported. Details on CPUID are
provided in the Cedar Mill Processor Family BIOS Writer’s Guide document and the
Intel
operate with the same front side bus frequency, core frequency and internal cache
sizes. Mixing processors operating at different internal clock frequencies is not
supported and will not be validated by Intel. Intel does not support or validate
operation of processors with different cache sizes. Mixing different processor steppings
but the same model (as per the CPUID instruction) is supported. Details on CPUID are
provided in the Cedar Mill Processor Family BIOS Writer’s Guide document and the
Intel
®
Processor Identification and the CPUID Instruction application note.
The Dual-Core Intel Xeon processor 7100 series does not support mixing of the 7110,
7120, 7130 or 7140 Processor Numbers. The Dual-Core Intel Xeon processor 7100
series does support mixing of the 7150 and 7140 Processor Numbers.
7120, 7130 or 7140 Processor Numbers. The Dual-Core Intel Xeon processor 7100
series does support mixing of the 7150 and 7140 Processor Numbers.
2.6
Front Side Bus Signal Groups
The front side bus signals are grouped by buffer type as listed in
. The buffer
type indicates which AC and DC specifications apply to the signals. AGTL+ input signals
have differential input buffers that use GTLREF as a reference level. In this document,
have differential input buffers that use GTLREF as a reference level. In this document,