Intel E6600 AT80571PH0832ML Scheda Tecnica
Codici prodotto
AT80571PH0832ML
Datasheet
19
Electrical Specifications
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep technology, or Extended HALT State).
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep technology, or Extended HALT State).
2.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
3.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See
event that a different voltage is required. See
and
for more
information.
4.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 M minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 M minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
5.
, for the minimum, typical, and maximum V
CC
allowed for a given
current. The processor should not be subjected to any V
CC
and I
CC
combination wherein
V
CC
exceeds V
CC_MAX
for a given current.
6.
I
CC_MAX
specification is based on V
CC_
MAX
loadline. See
for details.
7.
V
TT
must be provided using a separate voltage source and not be connected to V
CC
. This
specification is measured at the land.
8.
Baseboard bandwidth is limited to 20 MHz.
9.
This is the maximum total current drawn from the V
TT
plane by only the processor. This
specification does not include the current coming from on-board termination (R
TT
),
through the signal line. See the Voltage Regulator Design Guide to determine the total I
TT
drawn by the system. This parameter is based on design characterization and is not tested.
10.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
processor operation.
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
2.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. See
the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.
4.
Adherence to this loadline specification is required to ensure reliable processor operation.
Table 5.
Processor V
CC
Static and Transient Tolerance
I
CC
(A)
Voltage Deviation from VID Setting (V)
1, 2, 3, 4
Maximum Voltage
1.65 m
Typical Voltage
1.73 m
Minimum Voltage
1.80 m
0
0.000
-0.019
-0.038
5
-0.008
-0.028
-0.047
10
-0.017
-0.036
-0.056
15
-0.025
-0.045
-0.065
20
-0.033
-0.054
-0.074
25
-0.041
-0.062
-0.083
30
-0.050
-0.071
-0.092
35
-0.058
-0.079
-0.101
40
-0.066
-0.088
-0.110
45
-0.074
-0.097
-0.119
50
-0.083
-0.105
-0.128
55
-0.091
-0.114
-0.137
60
-0.099
-0.123
-0.146
65
-0.107
-0.131
-0.155
70
-0.116
-0.140
-0.164
75
-0.124
-0.148
-0.173