HP kp721av Manuale Utente

This chapter covers subjects dealing ICH10 with basic system architecture and covers the 
following topics: 

■

PCI bus overview (4.2)

■

System resources (4.3)

■

Real-time clock and configuration memory (4.4)

■

System management (4.5)

■

Register map and miscellaneous functions (4.6)

This chapter covers functions provided by off-the-shelf chipsets and therefore describes only 
basic aspects of these functions as well as information unique to the systems covered in this 
guide. For detailed information on specific components, refer to the applicable manufacturer's 
documentation. 

✎

This section describes the PCI bus in general and highlights bus implementation for systems 
covered in this guide. For detailed information regarding PCI bus operation, refer to the 
appropriate PCI specification or the PCI web site: www.pcisig.com.

These systems implement the following types of PCI buses:

■

PCI 2.3 - Legacy parallel interface operating at 33-MHz

■

PCI Express - High-performance interface capable of using multiple TX/RX high-speed 
lanes of serial data streams

The PCI 2.3 bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for 
handling both address and data transfers.  A bus transaction consists of an address cycle and one 
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is 
achieved during burst modes in which a transaction with contiguous memory locations requires 
that only one address cycle be conducted and subsequent data cycles are completed using 
auto-incremented addressing.

Devices on the PCI bus must comply with PCI protocol that allows configuration of that device 
by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus 
specification Rev. 2.3) is employed.