MiTAC 8050 Manuale Di Servizio
8050
8050
N/B Maintenance
N/B Maintenance
32
Compliant to PCI Revision 2.2Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back transaction
Provides PCI bus master data transfers and PCI
Memory space or I/O space mapped data transfers of RTL8100C(L)'s operational registers
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports 25MHz crystal or 25MHz OSC as the internal
Clock source. The frequency deviation of either crystal or OSC must be within 50 PPM.
Compliant to PC99/PC2001 standard
Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-
up frame)
Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)
Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still
remains off
PCI local bus single-chip Fast Ethernet controller