Motorola once sc140 Manuale Utente

Pagina di 28
2
Using the SC140 Enhanced OnCE Stopwatch Timer
2
SC140 Enhanced OnCE Stopwatch Timer 
Capabilities
This section presents the features of the Enhanced OnCE stopwatch timer and the resources required for 
implementation. The capabilities of the implementation of the stopwatch timer are also explained.
2.1   
Features
The Enhanced OnCE stopwatch timer provides the following features:
A 64-bit counter, incrementing on each DSP clock cycle. The counter is less susceptible to overflow 
with 64-bit precision.
The stopwatch timer can be used repeatedly during the execution of an application.
Conversion between clock cycles and absolute time, based on the operating clock frequency of the DSP, is 
described in Section 3.4, “Converting Cycles to Actual Time,” on page -6.
2.2   
Resources
The Enhanced OnCE stopwatch timer requires use of these resources:
One Enhanced OnCE event detector (of the six available on each DSP)
The Enhanced OnCE event counter
Program memory of 724 bytes
Because the Enhanced OnCE supports only one event counter, the stopwatch timer cannot be used if the 
event counter is required for other debugging purposes (such as; the set up of a debugger breakpoint that 
requires counting occurrences of events).
2.3   
Implementation
The stopwatch timer implementation allocates a variable in memory which serves as the target for memory 
write operations. The Enhanced OnCE event detector is set up to detect writes to this flag variable. When 
setting up of an Enhanced OnCE event detector to detect memory access operations, it is necessary to 
specify which of the two data memory buses should be “snooped”. Because the selection of the bus to be 
used is performed dynamically, the event detector is set up to snoop both buses (XABA or XABB). Upon 
detecting the write to the flag variable, the event detector enables the Enhanced OnCE event counter, 
which starts counting down.
The Enhanced OnCE event counter can be configured as either a 64-bit counter or a 32-bit counter. 
Configuring the counter to use 64-bits eliminates the danger of counter overflow, at a negligible extra cost.
To stop the stopwatch timer, an appropriate value is written into the Enhanced OnCE memory-mapped 
event counter control register. When this operation is completed, the cycle countdown halts. At this point it 
is possible to read out the values of the Enhanced OnCE event counter registers, and translate them into 
elapsed number of cycles, or elapsed absolute time.