IBM powerpc 750gx Manuale Utente
User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
gx_04.fm.(1.2)
March 27, 2006
March 27, 2006
Exceptions
Page 159 of 377
The IEEE floating-point exception mode bits (FE0 and FE1) together define whether floating-point exceptions
are handled precisely, imprecisely, or whether they are taken at all. As shown in Table 4-4, if either FE0 or
FE1 is set, the 750GX treats exceptions as precise. MSR bits are guaranteed to be written to SRR1 when the
first instruction of the exception handler is encountered. For further details, see Chapter 6, “Exceptions” of the
PowerPC Microprocessor Family: The Programming Environments Manual.
are handled precisely, imprecisely, or whether they are taken at all. As shown in Table 4-4, if either FE0 or
FE1 is set, the 750GX treats exceptions as precise. MSR bits are guaranteed to be written to SRR1 when the
first instruction of the exception handler is encountered. For further details, see Chapter 6, “Exceptions” of the
PowerPC Microprocessor Family: The Programming Environments Manual.
22
BE
Branch trace enable
0
The processor executes branch instructions normally.
1
The processor generates a branch-type trace exception when a branch instruc-
tion executes successfully.
tion executes successfully.
23
FE1
IEEE floating-point exception mode 1 (see Table 4-4 on page 160).
24
Reserved
Reserved.
25
IP
Exception prefix. The setting of this bit specifies whether an exception vector offset is
prefaced with Fs or 0s. In the following description, nnnnn is the offset of the exception.
0
prefaced with Fs or 0s. In the following description, nnnnn is the offset of the exception.
0
Exceptions are vectored to the physical address 0x000n_nnnn.
1
Exceptions are vectored to the physical address 0xFFFn_nnnn.
26
IR
Instruction address translation
0
Instruction address translation is disabled.
1
Instruction address translation is enabled.
For more information, see Chapter 5, Memory Management, on page 179.
27
DR
Data address translation
0
0
Data address translation is disabled.
1
Data address translation is enabled.
For more information, see Chapter 5, Memory Management, on page 179.
28
Reserved
Reserved. Full function
1
29
PM
Performance-monitor marked mode
0
Process is not a marked process.
1
Process is a marked process.
750GX–specific; defined as reserved by the PowerPC Architecture. For more information
about the performance monitor, see Section 4.5.13, Performance-Monitor Interrupt
(0x00F00), on page 172.
about the performance monitor, see Section 4.5.13, Performance-Monitor Interrupt
(0x00F00), on page 172.
30
RI
Indicates whether a system reset or machine-check exception is recoverable.
0
0
Exception is not recoverable.
1
Exception is recoverable.
The RI bit indicates whether, from the perspective of the processor, it is safe to continue
(that is, the processor state data such as that saved to SRR0 is valid), but it does not
guarantee that the interrupted process is recoverable. Exception handlers must look at bit
30 in SRR1 to determine if the interrupted process is recoverable.
(that is, the processor state data such as that saved to SRR0 is valid), but it does not
guarantee that the interrupted process is recoverable. Exception handlers must look at bit
30 in SRR1 to determine if the interrupted process is recoverable.
31 LE
Little-endian mode enable
0
The processor runs in big-endian mode.
1
The processor runs in little-endian mode.
Bits
Field Name
Description
1. Full function reserved bits are saved in SRR1 when an exception occurs; they are saved in the same bit locations in SRR1 that
they occupy in MSR. Partial function reserved bits are not saved.