NEC PD78P214 Manuale Utente

163

Chapter 7   Timer/Counter Units

When the value of CR20 or CR21 coincides with the value of TM2, timer output can be inverted.

By setting the higher 4 bits of the timer output control register (TOC), a square wave can be output on a timer
output pin (TO2, TO3).  At this time, PWM/PPG output is possible, depending on the setting of capture/
compare control register 2 (CRC2).

Timer output can be disabled or enabled by the TOC register.  When timer output is disabled, a fixed level is
output on the TO2 and TO3 pins.  (An output level is set using the TOC register.)

The prescaler generates count clocks from the internal system clock.  From these count clocks generated by
the prescaler, a count clock is selected with the selector for the timer to perform count operation.

The TMC1 register is an 8-bit register for controlling the count operations of 8-bit timer 1 (TM1) and 8-bit timer
2 (TM2).

The higher 4 bits control the count operation of TM2 of 8-bit timer/counter 2.  (The lower 4 bits control the count
operation of TM1 of 8-bit timer/counter 1.)

The TMC1 register allows both read and write operations using an 8-bit manipulation instruction.  Fig. 7-67
shows the format of the TMC1 register.

When the RESET signal is applied, the TMC1 register is cleared to 00H.

7

6

5

4

3

2

1

0

CE2

OVF2 CMD2

0

CE1

OVF1

0

0

TMC1

CMD2

0

1

1

0

CE2

TM2 operating mode specification

Normal mode

One-shot mode

TM2 counting control

Clears and stops counting

Enables counting

These bits control counting for TM1 of 8-bit 
timer/counter 1 (see Fig. 7-44).

OVF2 TM2 overflow flag

Overflow does not occur

Overflow occurs 
(counting up from FFH to 00H)

0

1

Remark  The OVF2 bit can be reset only by software.