NEC PD78P214 Manuale Utente
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Chapter 9 Asynchronous Serial Interface
9
(1) Reception buffer (RXB)
The reception buffer holds the receive data. Each time the shift register receives 1 byte of data, it sends it to
this reception buffer.
this reception buffer.
If the data length is specified to be 7 bits, the receive data is sent to bits 0 through 6 of the RXB. The MSB of
the RXB is always kept as 0.
the RXB is always kept as 0.
Only an 8-bit manipulation instruction can be used for the reception buffer, and its use is limited to read
operations. When the RESET signal is input, the contents of the RXB become undefined.
operations. When the RESET signal is input, the contents of the RXB become undefined.
(2) Transmission shift register (TXS)
The transmission shift register holds the data to be transmitted. The data written to the TXS is transmitted
as serial data.
as serial data.
If the data length is specified to be 7, bits 0 through 6 of the data written to the TXS register are treated as the
transmit data. Writing data to the TXS register triggers transmission. Do not write to the TXS register when
transmission is in progress.
transmit data. Writing data to the TXS register triggers transmission. Do not write to the TXS register when
transmission is in progress.
Only an 8-bit manipulation instruction can be used for the transmission shift register, and its use is limited
to write operations. When the RESET signal is input, the contents of the TXS become undefined.
to write operations. When the RESET signal is input, the contents of the TXS become undefined.
(3) Shift register
The shift register converts the serial data input to the RxD pin into parallel data. When it receives 1 byte of
data, it sends it to the reception buffer.
data, it sends it to the reception buffer.
The shift register cannot be manipulated directly from the CPU.
(4) Reception control parity check
Reception is controlled according to the contents of the asynchronous serial interface mode register (ASIM).
In addition, error checks such as parity error check are also performed during reception. If an error is detected,
a value corresponding to the error is set in the asynchronous serial interface status register (ASIS).
In addition, error checks such as parity error check are also performed during reception. If an error is detected,
a value corresponding to the error is set in the asynchronous serial interface status register (ASIS).
(5) Transmission control parity generation
Transmission is controlled by appending a start bit, parity bit, and one or two stop bits to the data written to
the TXS register according to the contents of the ASIM register.
the TXS register according to the contents of the ASIM register.
(6) Selector
The selector selects a baud rate clock source.
9.2 ASYNCHRONOUS SERIAL INTERFACE CONTROL REGISTER
(1) Asynchronous serial interface mode register (ASIM)
This 8-bit register specifies the asynchronous serial interface operations.
Either 8-bit manipulation instruction or a bit manipulation instruction can be used to read data from or write
data to this register. Fig. 9-2 shows the format of the asynchronous serial interface control register.
data to this register. Fig. 9-2 shows the format of the asynchronous serial interface control register.
When the RESET signal is input, the ASIM register is set to 80H.