NEC PD78P214 Manuale Utente
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Chapter 9 Asynchronous Serial Interface
9
9.3.4 Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, reception is enabled, and
the input to the RxD pin is sampled.
the input to the RxD pin is sampled.
Sampling at the RxD pin is performed using the serial clock specified in the ASIM register.
When the input to the RxD pin becomes low, the 1/16 frequency division counter starts counting. When the counter
reaches eight counts, it outputs the start timing signal for data sampling. The RxD pin is sampled with this start
timing signal again. If the pin is found to be at low level, it is recognized as a start bit, then initializing the 1/16
frequency division counter and causing it to start counting again for data sampling. When a start bit, data bits,
parity bit, and a stop bit Note are detected, reception of one frame of data is completed.
reaches eight counts, it outputs the start timing signal for data sampling. The RxD pin is sampled with this start
timing signal again. If the pin is found to be at low level, it is recognized as a start bit, then initializing the 1/16
frequency division counter and causing it to start counting again for data sampling. When a start bit, data bits,
parity bit, and a stop bit Note are detected, reception of one frame of data is completed.
When one frame of data is received, the receive data in the shift register is sent to the reception buffer (RXB),
eventually generating a reception completion interrupt (INTSR).
eventually generating a reception completion interrupt (INTSR).
If an error occurs, the erroneous receive data is sent to the RXB and causes an INTSR to be generated.
Resetting the RXE bit to 0 immediately stops reception. In this case, the contents of the RXB or ASIS are not
affected, and neither INTSR nor INTSER is generated. Setting the RXE bit to 1 triggers sampling for a start bit.
affected, and neither INTSR nor INTSER is generated. Setting the RXE bit to 1 triggers sampling for a start bit.
Note Reception assumes there is only one stop bit, regardless of whether the SL bit of the ASIM register is 1.
Fig. 9-6 Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
D6
Parity
D7
D2
D1
D0
START
RxD (Input)
INTSR
Cautions 1. If the ASIM register is modified during reception, the current and next receive data may be damaged. When changing the mode,
disable reception beforehand.
2. Be sure to read the reception buffer (RXB) contents, even if a reception error occurs. Otherwise, an overrun error will occur when
the next data is received, and the error status will persist.
9.3.5 Reception Error
Three types of errors may occur during reception; parity error, framing error, and overrun error. If any one of these
errors occurs, the corresponding error flag in the asynchronous serial interface register (ASIS) is set, and a
reception error interrupt (INTSER) is generated. Table 9-1 lists causes of reception errors.
errors occurs, the corresponding error flag in the asynchronous serial interface register (ASIS) is set, and a
reception error interrupt (INTSER) is generated. Table 9-1 lists causes of reception errors.
The type of the reception error can be identified by the reception error interrupt routine (INTSER), which reads and
checks the contents of the asynchronous serial interface register (ASIS). (See Fig. 9-3 and Fig. 9-7.)
checks the contents of the asynchronous serial interface register (ASIS). (See Fig. 9-3 and Fig. 9-7.)
The ASIS is reset to 0 by reading data from the reception buffer (RXB) or receiving the next data. (If the next data
again contains an error, the corresponding error flag will be set.)
again contains an error, the corresponding error flag will be set.)
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