NEC PD78P214 Manuale Utente

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Chapter 13   Local Bus Interface Function

The 

µPD78212, µPD78214, and µPD78P214 contain an internal ROM.  The internal ROM can be accessed quickly

without having to use the bus control circuit.  Usually, internal ROM is fetched at the same speed as external ROM.
When the IFCH bit of the memory expansion mode register (MM) is set to 1, the high-speed fetch function is
enabled, which can speed up internal ROM fetching.

When the same instruction execution cycle as that for external ROM fetching is selected, wait states are inserted
into the cycle by the wait function.  When high-speed fetching is performed, however, no wait state is inserted
when accessing internal ROM.

When the RESET signal is applied, the instruction execution cycle for internal fetching is the same as that for the
external ROM fetch cycle.

When a slow memory or I/O is connected to the 

µPD78214, wait states can be inserted into the external memory

access cycle.

Wait states are inserted while the RD or WR signal is low.  The low level period of the signal is extended by 1/f

CLK

(167 ns with f

CLK

 = 6 MHz) for each wait state.

There are two methods of inserting wait states:  Using the programmable wait function to automatically insert a
predefined number of wait states, and using an external wait signal to control wait insertion.

Wait state insertion is controlled with the memory expansion mode register (MM) for space 00000H to 0FFFFH and
the programmable wait control register (PW) for space 10000H to FFFFFH.  No wait state is inserted when internal
ROM and RAM are accessed upon high-speed fetching.  When the internal SFR area is accessed, wait states are
inserted at the appropriate timing, regardless of the register specification.

When an access to internal ROM is specified such that it will be performed in the same execution cycle as an access
to external ROM, wait states are also inserted into the internal ROM access cycle according to the MM register
setting.

When control with an external wait signal is specified by the MM register and/or the PW register, the WAIT signal
is applied to pin P66.

When the RESET signal is applied, pin P66 functions as a general-purpose I/O port pin.

Figs. 13-15 to 13-17 show the bus timings when wait states are inserted.