NEC PD78P214 Manuale Utente
379
Chapter 14 Standby Function
14
14.2 STANDBY CONTROL REGISTER (STBC)
The standby control register (STBC) is an 8-bit register which controls standby mode. The STBC register can be
both read and written. Only a specified instruction (MOV STBC, #byte), however, can be used for writing to the
register, to prevent the application system stopping unintentionally as a result of a program crash. Fig. 14-3 shows
the format of the STBC register.
both read and written. Only a specified instruction (MOV STBC, #byte), however, can be used for writing to the
register, to prevent the application system stopping unintentionally as a result of a program crash. Fig. 14-3 shows
the format of the STBC register.
When the RESET signal is input, the register is set to 0000
×000B.
Fig. 14-3 Configuration of the Standby Control Register (STBC)
14.3 HALT MODE
14.3.1 Specifying HALT Mode and Operation States in HALT Mode
The system enters HALT mode when the HLT bit of the STBC register is set to 1.
The STBC register can be written only with a specified 8-bit data write instruction. When specifying HALT mode,
execute the “MOV STBC, #01H” instruction.
execute the “MOV STBC, #01H” instruction.
Caution If HALT mode is specified under the conditions for releasing HALT mode, the system does not enter HALT mode, instead executing
the next instruction or branching to the vectored interrupt service program. Clear any interrupt requests before specifying HALT
mode to ensure that the system enters HALT mode correctly.
mode to ensure that the system enters HALT mode correctly.
Table 14-1 Operation States in HALT Mode
Clock oscillator
Internal system clock
CPU
I/O lines
Peripheral functions
Internal RAM
AD0-AD7
Bus lines
A8-A15
A16-A19
RD, WR output
ASTB output
Operating
Operating
Stopped
Note
Same as before HALT mode
Operating
Contents maintained
High-impedance
States maintained
Low
High
Low
Note Macro services are executed.
0
7
0
6
0
5
0
4
×
3
0
2
STP
1
HLT
0
STBC
When this bit is set to 1, HALT mode is set.
This bit is automatically reset to 0 when HALT mode is released.
This bit is automatically reset to 0 when HALT mode is released.
HALT mode specification bit
When this bit is set to 1, STOP mode is set.
This bit is automatically reset to 0 when STOP mode is released.
This bit is automatically reset to 0 when STOP mode is released.
STOP mode specification bit
×: 0 or 1