NEC PD750004 Manuale Utente

The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the

clock to be output to the SCK pin when the internal system clock is used.

The busy/acknowledge output circuit and bus release/command/acknowledge detection circuit output and

detect control signals generated in the SBI mode.

These circuits do not operate in the three-wire or two-wire serial I/O mode.

The P01 output latch generates serial clock by software after the eighth serial clock has been output.

When the RESET signal is entered, this latch is set to 1.

To select the internal system clock as the serial clock, set the P01 output latch to 1.

Figure 5-40 shows the format of serial operation mode register (CSIM).

CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function,

and so forth.

CSIM is manipulated using an 8-bit memory manipulation instruction.  The higher three bits can be

manipulated bit by bit.  Each bit can be manipulated using its name.

Each bit may or may not allow read and/or write operation (see Figure 5-40).  Bit 6 allows bit test operation

only; any data written to this bit is invalid.

When the RESET signal is generated, all bits are cleared to 0.

Remarks 1. (R) :  Read only

2. (W):  Write only

CSIE

COI

WUP

CSIM4

CSIM3

CSIM1

CSIM2

CSIM0

7

6

5

4

3

1

2

0

Address

CSIM

Symbol

Serial clock selection bit (W)

FE0H

Serial interface operation enable/disable specification bit (W)

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Signal from address comparator (R)