NEC PD78078 Manuale Utente
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078 SUBSERIES)
318
17.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 17-2. Serial Interface Channel 0 Configuration
Item
Configuration
Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Control register
Serial bus interface control register (SBIC)
Interrupt timing specify register (SINT)
Port mode register 2 (PM2)
Note
Note
Refer to Figure 6-5 Block Diagram of P20, P21, P23 to P26 and Figure 6-6 Block
Diagram of P22 and P27.
Figure 17-2. Serial Interface Channel 0 Block Diagram
Remark
Output control selects either CMOS output or N-ch open drain output.
Register
CSIE0 COI
WUP
CSIM
04
CSIM
03
CSIM
02
CSIM
01
CSIM
00
Serial Operating
Mode Register 0
Control
Circuit
Output
Control
Selector
SI0/SB0
/P25
PM25
Output
Control
SO0/SB1
/P26
PM26
Output
Control
SCK0
/P27
PM27
Selector
P25
Output
Latch
Output
Latch
P26 Output
Latch
Latch
CLD
P27
Output Latch
Internal Bus
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Internal Bus
Slave Address
Register (SVA)
Serial I/O Shift
Register 0 (SIO0)
Bus Release/
Command/
Acknowledge
Detector
Serial Clock
Counter
Serial Clock
Control Circuit
CLR
D
SET
Q
Match
Busy/
Acknowledge
Output Circuit
Interrupt
Request Signal
Generator
ACKD
CMDD
RELD
CMDD
RELD
WUP
Selector
Selector
CLD
SIC SVAM
TCL33 TCL32 TCL31 TCL30
4
CSIM01
CSIM00
CSIM01
CSIM00
TO2
Interrupt Timing
Specify Register
Timer Clock Select
Register 3
f
xx
/2 to f
xx
/2
8
INTCSI0
Serial Bus Interface
Control Register
Control Register
SVAM